cordic_par_seq_apb_modport_tf.v

systemverilog程序

`timescale 1ns/1ns

module CORDIC_par_seq_modport_tb;

  parameter
    DUT_IObase    = 16'hFE00,
    ClockPeriod   = 10,
    TimeoutCycles = 30;

  initial
    $timeformat (-9, 0, "ns", 8);

  // Interconnect

  // (1) Global asynch reset:
  //
  logic async_reset;

  // (2) APB bus:
  //
  APB
    #(.master_Tco(1.5))
    theBus ( );

  // DUT
  //
  CORDIC_par_seq_APB
    #(.baseAddress(DUT_IObase))
    DUT (.bus(theBus.RTL_slave), .*);

  // Test master - this is a bus master that provides various
  // utility tasks including the ability to load and read all
  // the CORDIC device's registers over the bus.  I wanted
  // this module to call BFM tasks imported from the interface,
  // but VCS won't let me use any interactive features if I do that.
  // Hence the BFM tasks have been copied into this module, which
  // hooks to APB via its RTL_master modport (instead of TF_master).
  //
  CORDIC_par_seq_bus_test_master_RTL
    #(
      .period     (ClockPeriod),
      .master_Tco (1.5)
    )
    TestMaster (.apb(theBus.RTL_master));

  // Now the test case...
  CORDIC_par_seq_APB_testcase
    #(
      .IObase         (DUT_IObase),
      .timeout        (ClockPeriod * TimeoutCycles),
      .TestIterations (20)
    )
    TestCase ();

endmodule // CORDIC_par_seq_modport_tb