fail.v

来自「systemverilog程序」· Verilog 代码 · 共 53 行

// ________________________________________________________________ fail.v ___


`timescale 1ns/100ps


module testit(input logic PCLK, input logic psel, input logic PENABLE);

  always @(posedge PCLK) $display("psel, PENABLE = {%b,%b}", psel, PENABLE);

  sequence CYCLE_SEQ;
    @(posedge PCLK) (psel && !PENABLE) ##1 (psel && PENABLE);
  endsequence

  property RESTART;
    @(posedge PCLK) CYCLE_SEQ.ended |=> (!PENABLE);
  endproperty
  //

  //cover  property (CYCLE_SEQ);
  assert property (RESTART);

// __________________________________________________________________________


endmodule // testit




module testfail;

  logic c, s, e;

  testit dut(c, s, e);

  initial begin : clkgen
    #5 c = 0;
    repeat (200) #5 c = ~c;
  end

  initial begin : stimgen
    integer seed;
    seed = 1;
    forever @(negedge c) begin
      {s, e} = $dist_uniform(seed, 0, 3);
    end
  end

endmodule