machinectl.v

来自「verilog source crc criteria, such as CYX」· Verilog 代码 · 共 17 行

//?????
//------------------------------------------------------------------------------
module machinectl( ena, fetch, rst);
output  ena;
input  fetch, rst;
reg ena;

always @(posedge fetch or posedge rst)
begin
if(rst)
ena<=0;
else
ena<=1;
end

endmodule
//----------------------------------------------------------------------------