div.tan.rpt

FPGA调试程序

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 75.19 MHz between source register "count[1]" and destination register "count[31]" (period= 13.3 ns)
    Info: + Longest register to register delay is 12.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E3; Fanout = 3; REG Node = 'count[1]'
        Info: 2: + IC(0.900 ns) + CELL(0.700 ns) = 1.600 ns; Loc. = LC2_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.800 ns; Loc. = LC3_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 2.000 ns; Loc. = LC4_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 2.200 ns; Loc. = LC5_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 2.400 ns; Loc. = LC6_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 2.600 ns; Loc. = LC7_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 2.800 ns; Loc. = LC8_E2; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]'
        Info: 9: + IC(0.500 ns) + CELL(0.200 ns) = 3.500 ns; Loc. = LC1_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]'
        Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 3.700 ns; Loc. = LC2_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]'
        Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 3.900 ns; Loc. = LC3_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10]'
        Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 4.100 ns; Loc. = LC4_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11]'
        Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 4.300 ns; Loc. = LC5_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12]'
        Info: 14: + IC(0.000 ns) + CELL(0.200 ns) = 4.500 ns; Loc. = LC6_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13]'
        Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 4.700 ns; Loc. = LC7_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14]'
        Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 4.900 ns; Loc. = LC8_E4; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[15]'
        Info: 17: + IC(0.500 ns) + CELL(0.200 ns) = 5.600 ns; Loc. = LC1_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[16]'
        Info: 18: + IC(0.000 ns) + CELL(0.200 ns) = 5.800 ns; Loc. = LC2_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[17]'
        Info: 19: + IC(0.000 ns) + CELL(0.200 ns) = 6.000 ns; Loc. = LC3_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[18]'
        Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 6.200 ns; Loc. = LC4_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[19]'
        Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 6.400 ns; Loc. = LC5_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[20]'
        Info: 22: + IC(0.000 ns) + CELL(0.200 ns) = 6.600 ns; Loc. = LC6_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[21]'
        Info: 23: + IC(0.000 ns) + CELL(0.200 ns) = 6.800 ns; Loc. = LC7_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[22]'
        Info: 24: + IC(0.000 ns) + CELL(0.200 ns) = 7.000 ns; Loc. = LC8_E6; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[23]'
        Info: 25: + IC(0.500 ns) + CELL(0.200 ns) = 7.700 ns; Loc. = LC1_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[24]'
        Info: 26: + IC(0.000 ns) + CELL(0.200 ns) = 7.900 ns; Loc. = LC2_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[25]'
        Info: 27: + IC(0.000 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = LC3_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[26]'
        Info: 28: + IC(0.000 ns) + CELL(0.200 ns) = 8.300 ns; Loc. = LC4_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[27]'
        Info: 29: + IC(0.000 ns) + CELL(0.200 ns) = 8.500 ns; Loc. = LC5_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[28]'
        Info: 30: + IC(0.000 ns) + CELL(0.200 ns) = 8.700 ns; Loc. = LC6_E8; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[29]'
        Info: 31: + IC(0.000 ns) + CELL(0.200 ns) = 8.900 ns; Loc. = LC7_E8; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[30]'
        Info: 32: + IC(0.000 ns) + CELL(1.400 ns) = 10.300 ns; Loc. = LC8_E8; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder|unreg_res_node[31]'
        Info: 33: + IC(1.100 ns) + CELL(0.800 ns) = 12.200 ns; Loc. = LC1_E10; Fanout = 2; REG Node = 'count[31]'
        Info: Total cell delay = 8.700 ns ( 71.31 % )
        Info: Total interconnect delay = 3.500 ns ( 28.69 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 38; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E10; Fanout = 2; REG Node = 'count[31]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 38; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E3; Fanout = 3; REG Node = 'count[1]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "leda[5]" through register "leda[0]~6" is 9.900 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 38; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 1; REG Node = 'leda[0]~6'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E36; Fanout = 1; REG Node = 'leda[0]~6'
        Info: 2: + IC(0.700 ns) + CELL(6.300 ns) = 7.000 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'leda[5]'
        Info: Total cell delay = 6.300 ns ( 90.00 % )
        Info: Total interconnect delay = 0.700 ns ( 10.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Tue Nov 25 10:38:13 2008
    Info: Elapsed time: 00:00:01