test1.map.summary

来自「实现任意倍数的倍频,帮助大家解决VHDL倍频问题,」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Mon Apr 07 12:41:43 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Web Edition
Revision Name : test1
Top-level Entity Name : test1
Family : Stratix
Met timing requirements : N/A
Total logic elements : 0
Total pins : 16
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0