test1.fit.qmsg

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,

{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.30 8 8 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 29 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "8 " "Warning: The following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[0\] GND " "Info: Pin d\[0\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[0\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[0] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[1\] GND " "Info: Pin d\[1\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[1\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[1] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[2\] GND " "Info: Pin d\[2\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[2\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[2] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[3\] GND " "Info: Pin d\[3\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[3\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[3] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[4\] GND " "Info: Pin d\[4\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[4\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[4] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[5\] GND " "Info: Pin d\[5\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[5\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[5] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[6\] GND " "Info: Pin d\[6\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[6\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[6] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[7\] GND " "Info: Pin d\[7\] has GND driving its datain port" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[7\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[7] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 07 12:42:16 2008 " "Info: Processing ended: Mon Apr 07 12:42:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0}  } {  } 0}