test1.fit.qmsg

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Web Edition " "Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 07 12:41:47 2008 " "Info: Processing started: Mon Apr 07 12:41:47 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off test -c test1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test1" {  } {  } 0}
{ "Info" "IMPP_MPP_AVAILABLE_IO_STANDARD_IN_DEVICE" "EP1S10F484C5 " "Info: Auto device selection -- successful I/O standard check for EP1S10F484C5" {  } {  } 0}
{ "Info" "IMPP_MPP_AVAILABLE_PCI_IO_IN_DEVICE" "EP1S10F484C5 " "Info: Auto device selection -- successful PCI I/O clamp diode check for EP1S10F484C5" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "test1 EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design test1" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "16 16 " "Info: No exact pin location assignment(s) for 16 pins of 16 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[0\] " "Info: Pin a\[0\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[0\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[0] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[1\] " "Info: Pin a\[1\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[1\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[1] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[2\] " "Info: Pin a\[2\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[2\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[2] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[3\] " "Info: Pin a\[3\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[3\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[3] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[4\] " "Info: Pin a\[4\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[4\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[4] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[5\] " "Info: Pin a\[5\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[5\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[5] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[6\] " "Info: Pin a\[6\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[6\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[6] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[7\] " "Info: Pin a\[7\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a\[7\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { a[7] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { a[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[0\] " "Info: Pin d\[0\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[0\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[0] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[1\] " "Info: Pin d\[1\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[1\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[1] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[2\] " "Info: Pin d\[2\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[2\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[2] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[3\] " "Info: Pin d\[3\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[3\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[3] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[4\] " "Info: Pin d\[4\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[4\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[4] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[5\] " "Info: Pin d\[5\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[5\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[5] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[6\] " "Info: Pin d\[6\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[6\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[6] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[7\] " "Info: Pin d\[7\] not assigned to an exact location on the device" {  } { { "test1.vhd" "" { Text "F:/FPGA/test/test1.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "d\[7\]" } } } } { "F:/FPGA/test/db/test1_cmp.qrpt" "" { Report "F:/FPGA/test/db/test1_cmp.qrpt" Compiler "test1" "UNKNOWN" "V1" "F:/FPGA/test/db/test.quartus_db" { Floorplan "F:/FPGA/test/" "" "" { d[7] } "NODE_NAME" } "" } } { "F:/FPGA/test/test1.fld" "" { Floorplan "F:/FPGA/test/test1.fld" "" "" { d[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}