📄 test1.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--a[0] is a[0]
--operation mode is input
a[0] = INPUT();
--a[1] is a[1]
--operation mode is input
a[1] = INPUT();
--a[2] is a[2]
--operation mode is input
a[2] = INPUT();
--a[3] is a[3]
--operation mode is input
a[3] = INPUT();
--a[4] is a[4]
--operation mode is input
a[4] = INPUT();
--a[5] is a[5]
--operation mode is input
a[5] = INPUT();
--a[6] is a[6]
--operation mode is input
a[6] = INPUT();
--a[7] is a[7]
--operation mode is input
a[7] = INPUT();
--d[0] is d[0]
--operation mode is output
d[0] = OUTPUT(VCC);
--d[1] is d[1]
--operation mode is output
d[1] = OUTPUT(VCC);
--d[2] is d[2]
--operation mode is output
d[2] = OUTPUT(GND);
--d[3] is d[3]
--operation mode is output
d[3] = OUTPUT(GND);
--d[4] is d[4]
--operation mode is output
d[4] = OUTPUT(VCC);
--d[5] is d[5]
--operation mode is output
d[5] = OUTPUT(GND);
--d[6] is d[6]
--operation mode is output
d[6] = OUTPUT(VCC);
--d[7] is d[7]
--operation mode is output
d[7] = OUTPUT(GND);
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