test1.vhd

来自「实现任意倍数的倍频,帮助大家解决VHDL倍频问题,」· VHDL 代码 · 共 26 行

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 

entity test1 is
	port
	(
		a:in std_logic_vector(7 downto 0);
		--b:in std_logic_vector(0 to 7);
				d:out std_logic_vector(7 downto 0)
					--	e:out std_logic_vector(0 to 7)
	);
end test1;

architecture test_a of test1 is
signal f: std_logic_vector(7 downto 0);
begin
	process(a)
	begin
	f<="01010011";
	d<=f;
	end process;
end;