📄 test1.map.talkback.xml
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<!--
This XML file (created on Mon Apr 07 12:41:43 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
<nic_id>00e04c71b683</nic_id>
<cdrive_id>205b19dd</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.0</version>
<build>Build 148</build>
<module>quartus_map.exe</module>
<edition>Web Edition (Eval)</edition>
<compilation_end_time>Mon Apr 07 12:41:43 2008</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">849</cpu_freq>
</cpu>
<ram units="MB">512</ram>
</machine>
<top_file>F:/FPGA/test/test1</top_file>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off test -c test1</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Design contains 8 input pin(s) that do not drive logic</warning>
<warning>Warning: No output dependent on input pin "a[7]"</warning>
<warning>Warning: No output dependent on input pin "a[6]"</warning>
<warning>Warning: No output dependent on input pin "a[5]"</warning>
<warning>Warning: No output dependent on input pin "a[4]"</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings</info>
<info>Info: Elapsed time: 00:00:05</info>
<info>Info: Processing ended: Mon Apr 07 12:41:43 2008</info>
<info>Info: Implemented 16 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 8 output pins</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Top-level entity name</option>
<setting>test1</setting>
<default_value>test1</default_value>
</row>
<row>
<option>Family name</option>
<setting>Stratix</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Restructure Multiplexers</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>off</setting>
<default_value>off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>DSP Block Balancing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Maximum DSP Block Usage</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- Stratix/Stratix GX</option>
<setting>Balanced</setting>
<default_value>Balanced</default_value>
</row>
<row>
<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
<setting>70</setting>
<default_value>70</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Perform WYSIWYG Primitive Resynthesis</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform gate-level register retiming</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto ROM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto DSP Block Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Shift Register Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Allows Synchronous Control Signal Usage in Normal Mode Logic Cells</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Block Balancing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any RAM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any ROM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any Shift Register Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Maximum Number of M512 Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Maximum Number of M4K Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Maximum Number of M-RAM Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
</analysis___synthesis_settings>
<general_register_statistics>
<row>
<statistic>Total registers</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Synchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Synchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Clock Enable</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Preset</statistic>
<value>0</value>
</row>
</general_register_statistics>
<compilation_summary>
<flow_status>Successful - Mon Apr 07 12:41:43 2008</flow_status>
<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Web Edition</quartus_ii_version>
<revision_name>test1</revision_name>
<top_level_entity_name>test1</top_level_entity_name>
<family>Stratix</family>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>0</total_logic_elements>
<total_pins>16</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>0</total_memory_bits>
<dsp_block_9_bit_elements>0</dsp_block_9_bit_elements>
<total_plls>0</total_plls>
<total_dlls>0</total_dlls>
</compilation_summary>
<compile_id>51D4FFC9</compile_id>
</talkback>
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