addac.v

some example for verilog design

//Implicit style addition by bit serial
//copyright 1997 Mark Arnold
//all rights reserved

//need to use following for simulation with VeriWell
`define CLK @(posedge sysclk)
`define ENS #1

//need to use following for synthesis by Synopsys:
//`define CLK
//`define ENS

`define NUM_SYS_BITS   4

module vsyadd1(pb,ready,x,y,r1,r2,reset,sysclk);
  input pb;
  input [`NUM_SYS_BITS-1:0] x,y;
  input reset,sysclk;
  output ready;
  output [`NUM_SYS_BITS-1:0] r1,r2;

  wire reset,sysclk;
  wire pb;
  wire [`NUM_SYS_BITS-1:0] x,y;
  reg ready;
  reg [`NUM_SYS_BITS-1:0] r1,r2,r3;
  reg c;

  function car;
    input a,b,c;
    begin
      car = a&b|a&c|b&c;
    end
  endfunction

  function sum;
    input a,b,c;
    begin
      sum = a+b+c;
    end
  endfunction

  always
    begin
        ready <= `CLK 1;
      @(posedge sysclk) `ENS;
        r2 <= `CLK y;
        r3 <= `CLK 1;
        c <= `CLK 0;
        if (pb)
          begin
              ready <= @(posedge sysclk) 0;
            @(posedge sysclk)`ENS;
              r1 <= `CLK x;
              while (~r3[`NUM_SYS_BITS-1])
                begin
                  @(posedge sysclk) `ENS;
                    r1 <= `CLK {sum(r1[0],r2[0],c),r1[`NUM_SYS_BITS-1:1]};
                    c  <= `CLK car(r1[0],r2[0],c);
                    r2 <= `CLK r2 >> 1;
                    r3 <= `CLK r3 << 1;
                end
          end
    end
endmodule

module debounce(sw3,pb,cnt,sysclk,reset);
  input sw3,sysclk,reset;
  output pb;
  output [19:0] cnt;

  wire sw3,sysclk,reset;
  reg pb;
  reg [19:0] cnt;
  
  always
    begin
      @(posedge sysclk) `ENS;
        pb <= `CLK 0;
        if (sw3 == 1)
          cnt <= `CLK 20'hfffff;
        else
          while (cnt[19:1] != 0)
            begin
              @(posedge sysclk) `ENS;
                if (sw3 == 0)
                  cnt <= `CLK cnt - 1;
                if (cnt[19:1] == 0)
                  pb <= `CLK 1;
            end
    end
endmodule



module mach445(sw3,sw2,sw1,sw0,sysclk,reset,
             a1,b1,c1,d1,e1,f1,g1
      //       a2,b2,c2,d2,e2,f2,g2
             );

  input sw3,sw2,sw1,sw0,sysclk,reset;
  output a1,b1,c1,d1,e1,f1,g1;
//  output a2,b2,c2,d2,e2,f2,g2;

  wire sw3,sw2,sw1,sw0,sysclk,reset;
  reg a1,b1,c1,d1,e1,f1,g1;
//  reg a2,b2,c2,d2,e2,f2,g2;

//  row1 .a.
//  row2 f.b
//  row3 .g.
//  row4 e.c
//  row5 .d.

  function [7:0] seven_seg;
    input [3:0] i;
    reg [2:0] row1,row2,row3,row4,row5;
    reg a1,b,c,d1,e,f,g1;
    begin
      case (i)
        0: begin
             row1 = 3'b111;
             row2 = 3'b101;
             row3 = 3'b101;
             row4 = 3'b101;
             row5 = 3'b111;
           end
        1: begin
             row1 = 3'b001;
             row2 = 3'b001;
             row3 = 3'b001;
             row4 = 3'b001;
             row5 = 3'b001;
           end
        2: begin
             row1 = 3'b111;
             row2 = 3'b001;
             row3 = 3'b111;
             row4 = 3'b100;
             row5 = 3'b111;
           end
        3: begin
             row1 = 3'b111;
             row2 = 3'b001;
             row3 = 3'b111;
             row4 = 3'b001;
             row5 = 3'b111;
           end
        4: begin
             row1 = 3'b101;
             row2 = 3'b101;
             row3 = 3'b111;
             row4 = 3'b001;
             row5 = 3'b001;
           end
        5: begin
             row1 = 3'b111;
             row2 = 3'b100;
             row3 = 3'b111;
             row4 = 3'b001;
             row5 = 3'b111;
           end
        6: begin
             row1 = 3'b111;
             row2 = 3'b100;
             row3 = 3'b111;
             row4 = 3'b101;
             row5 = 3'b111;
           end
        7: begin
             row1 = 3'b111;
             row2 = 3'b001;
             row3 = 3'b001;
             row4 = 3'b001;
             row5 = 3'b001;
           end
        8: begin
             row1 = 3'b111;
             row2 = 3'b101;
             row3 = 3'b111;
             row4 = 3'b101;
             row5 = 3'b111;
           end
        9: begin
             row1 = 3'b111;
             row2 = 3'b101;
             row3 = 3'b111;
             row4 = 3'b001;
             row5 = 3'b001;
           end
        4'ha: begin
             row1 = 3'b111;
             row2 = 3'b101;
             row3 = 3'b111;
             row4 = 3'b101;
             row5 = 3'b101;
           end
        4'hb: begin
             row1 = 3'b100;
             row2 = 3'b100;
             row3 = 3'b111;
             row4 = 3'b101;
             row5 = 3'b111;
           end
        4'hc: begin
             row1 = 3'b111;
             row2 = 3'b100;
             row3 = 3'b100;
             row4 = 3'b100;
             row5 = 3'b111;
           end
        4'hd: begin
             row1 = 3'b001;
             row2 = 3'b001;
             row3 = 3'b111;
             row4 = 3'b101;
             row5 = 3'b111;
           end
        4'he: begin
             row1 = 3'b111;
             row2 = 3'b100;
             row3 = 3'b111;
             row4 = 3'b100;
             row5 = 3'b111;
           end
        4'hf: begin
             row1 = 3'b111;
             row2 = 3'b100;
             row3 = 3'b111;
             row4 = 3'b100;
             row5 = 3'b100;
           end
        default:
            begin
             row1 = 3'b000;
             row2 = 3'b000;
             row3 = 3'b000;
             row4 = 3'b000;
             row5 = 3'b000;
           end
      endcase
      a1 = row1[1];
      b = row2[0];
      f = row2[2];
      g1 = row3[1];
      c = row4[0];
      e = row4[2];
      d1 = row5[1];
      seven_seg = {a1,b,c,d1,e,f,g1};
    end
  endfunction

  wire ready;
  wire [3:0] r1,r2;
  reg [3:0] y;
  wire pb;
  wire [19:0] cnt;

  vsyadd1 v1(pb,ready,r1,y,r1,r2,reset,sysclk);
  debounce deb1(sw3,pb,cnt,sysclk,reset);

  always @(sw2 or sw1 or sw0)
    y = {sw2,sw1,sw0};

  always @(r1)
    {a1,b1,c1,d1,e1,f1,g1} = ~seven_seg(r1);

//  always @(r2)
//    {a2,b2,c2,d2,e2,f2,g2} = ~seven_seg(r2);
endmodule