utopia.vhd

utopia接口模块VHDL源码,实现UTOPIA接口功能,可进行UTOPIA接口仿真

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity UTOPIA is  -- slave mode 
  generic(
    fifo_width    :   integer := 32;
    status_bit    :   integer := 4;
    Pclass        :   integer := 4;
    clock_syn     :   boolean := true 
  );
  Port (
    utopia_clk    : in  std_logic;
    sysclk        : in  std_logic;
    reset         : in  std_logic;
    txaddr        : in  std_logic_vector(4 downto 0);
    txenb         : in  std_logic;
    txclav        : out std_logic;
    txclaven      : out std_logic;
    txdata        : out std_logic_vector(7 downto 0);   
    txdataen      : out std_logic;
    txsoc         : out std_logic;
    txsocen       : out std_logic;  
    txCellfull    : out std_logic_vector(Pclass - 1 downto 0);
    txCelldatain  : in  std_logic_vector(fifo_width + status_bit - 1  downto 0);
    txCellwren    : in  std_logic_vector(Pclass - 1 downto 0);
    txCellwrsoc   : in  std_logic;
    txCellwreoc   : in  std_logic;
    rxdata        : in  std_logic_vector(7 downto 0);
    rxenb         : in  std_logic;
    rxsoc         : in  std_logic;
    rxclav        : out std_logic;
    rxclaven      : out std_logic; 
    rxaddr        : in  std_logic_vector(4 downto 0);  
    rxCellempty   : out std_logic;
    rxCelldataout : out std_logic_vector(fifo_width + status_bit - 1  downto 0);
    rxCellrden    : in  std_logic;
    rxCellrdsoc   : in  std_logic;
    rxCellrdeoc   : in  std_logic;  
    timerset      : in  std_logic_vector((Pclass * 16) - 1 downto 0);  
    phyaddr       : in  std_logic_vector(4 downto 0);
    cha           : in  std_logic_vector(7 downto 0)    
  );
end UTOPIA;

architecture Behavioral of UTOPIA is

  component TranslateToUTOPIA is  -- slave mode 
  generic(
    fifo_width: integer := 32;
    Pclass    : integer := 5;
    clock_syn : boolean := true     
  );
  Port (  
    reset     : in  std_logic;
    txclk     : in  std_logic;  
    sysclk    : in  std_logic;
    txaddr    : in  std_logic_vector(4 downto 0);
    txenb     : in  std_logic;
    txclav    : out std_logic;
    txclaven  : out std_logic;
    txdata    : out std_logic_vector(7 downto 0);   
    txdataen  : out std_logic;
    txsoc     : out std_logic;
    txsocen   : out std_logic;  
    rbe       : in  std_logic_vector(Pclass - 1 downto 0);  
    rdd       : in  std_logic_vector(fifo_width - 1 downto 0);
    rdeop     : out std_logic;  
    rden      : out std_logic;   
    rdport    : out std_logic_vector(Pclass - 1 downto 0);   
    timerset  : in  std_logic_vector((Pclass * 16) - 1 downto 0);                     
    phyaddr   : in  std_logic_vector(4 downto 0)
  );
  end component;

  component ReceiveFromUTOPIA is -- slave mode
   generic (
     fifo_width : integer := 32;
     clock_syn  : boolean := true
   );
   Port (
     reset		  : in	std_logic;   
     rxclk		  : in	std_logic;
     sysclk     : in  std_logic;
	   rxdata  	  : in  std_logic_vector(7 downto 0);
     rxenb   	  : in  std_logic;
     rxsoc   	  : in  std_logic;
     rxclav  	  : out std_logic;
	   rxclaven 	: out std_logic; 
	   rxaddr   	: in  std_logic_vector(4 downto 0);     
	   wbf	      : in	std_logic;
	   wren  	    : out std_logic;
	   wrsop      : out std_logic;
     wreop 	    : out std_logic;
     wrd	      : out std_logic_vector(31 downto 0);     
	   phyaddr  	: in 	std_logic_vector(4 downto 0);
	   cha        : in  std_logic_vector(7 downto 0)
  );
  end component;

  component FIFO is
  generic(
    fifowidth   : integer := 32;
    packS       : integer := 4;
    packDepth   : integer := 512;
    status_bit  : integer := 4;
    bram_size   : integer := 16384;    
    eop_add     : boolean := true;
    info_loc    : integer := 4;
    wrclkeqrdclk: boolean := false;    
    wrclkgtrdclk: boolean := true
  );
  port(
    reset       : in  std_logic;    
    wrclk       : in  std_logic;
    rdclk       : in  std_logic;
    wrsop       : in  std_logic;
    wrsopt      : in  std_logic;
    wren        : in  std_logic;
    wreop       : in  std_logic;
    wrd         : in  std_logic_vector(fifowidth + status_bit - 1 downto 0);
    rdsop       : in  std_logic;
    rden        : in  std_logic;
    rdeop       : in  std_logic;
    rdd         : out std_logic_vector(fifowidth + status_bit - 1 downto 0);
    rbe         : out std_logic;
    wbf         : out std_logic
  );
  end component;

  signal txrden    : std_logic;
  signal txrdeoc   : std_logic;
  signal txrdport  : std_logic_vector(Pclass - 1 downto 0);
  signal txbufempty: std_logic_vector(Pclass - 1 downto 0);
  signal txwbf     : std_logic_vector(Pclass - 1 downto 0);
  signal txdataout : std_logic_vector(fifo_width - 1 downto 0);
  signal txwren    : std_logic_vector(Pclass - 1 downto 0);
  signal txcellrden: std_logic_vector(Pclass - 1 downto 0);
  signal rxwren    : std_logic;
  signal rxwreoc   : std_logic;
  signal rxrdd     : std_logic_vector(fifo_width + status_bit - 1 downto 0);
  signal rxwbf     : std_logic;
  signal rxbufempty: std_logic;
  type txdatatype is array(Pclass downto 0) of std_logic_vector(fifo_width + status_bit - 1 downto 0);
  signal txbufdataout : txdatatype;
  signal wrclk,rdclk  : std_logic;

begin

  txCellfull    <= txwbf(Pclass - 1 downto 0);
  txwren        <= txcellwren;
  label1 : if clock_syn = true generate
  begin
    wrclk       <= sysclk;
    rdclk       <= sysclk;
  end generate;  
  label2 : if clock_syn /= true generate
  begin
    wrclk       <= utopia_clk;
    rdclk       <= utopia_clk;
  end generate;    
  process(txrden,txrdport)
  begin
    for i in 0 to Pclass - 1 loop
      txcellrden(i)  <= txrden and txrdport(i);
    end loop;
  end process;

  process(rdclk)
  begin
    if rdclk'event and rdclk = '1' then
      if reset = '1' then
        txdataout     <= (others=>'0');
      else
        for i in 0 to Pclass - 1 loop
          if txrdport(i) = '1' then
            txdataout <= txbufdataout(i)(fifo_width - 1 downto 0);
            exit;
          end if;
        end loop;
      end if;
    end if;
  end process;

  label3 : for i in 0 to Pclass - 1 generate
  TX_BUF : FIFO
  generic map(
    FIFOWIDTH   => fifo_width,
    packS       => 32,
    PackDepth   => 16,
    status_bit  => status_bit,
    bram_size   => 16384,
    eop_add     => true,
    info_loc    => 0,
    wrclkeqrdclk=> clock_syn,
    wrclkgtrdclk=> true
  )
  port map(
    reset       => reset,
    wrclk       => sysclk,
    rdclk       => rdclk,
    wrsop       => txCellwrsoc,
    wrsopt      => '0',
    wren        => txwren(i),
    wreop       => txCellwreoc,
    wrd         => txCelldatain,
    rdsop       => '0',
    rden        => txCellrden(i),
    rdeop       => txrdeoc,
    rdd         => txbufdataout(i),
    rbe         => txbufempty(i),
    wbf         => txwbf(i)
  );  
  end generate;

  RX_BUF : FIFO
  generic map(
    FIFOWIDTH   => fifo_width,
    packS       => 32,
    PackDepth   => 16,
    status_bit  => status_bit,
    bram_size   => 16384,
    eop_add     => true,
    info_loc    => 0,
    wrclkeqrdclk=> clock_syn,
    wrclkgtrdclk=> false
  )
  port map(
    reset       => reset,
    wrclk       => wrclk,
    rdclk       => sysclk,
    wrsop       => '0',
    wrsopt      => '0',
    wren        => rxwren,
    wreop       => rxwreoc,
    wrd         => rxrdd,
    rdsop       => rxcellrdsoc,
    rden        => rxcellrden,
    rdeop       => rxcellrdeoc,
    rdd         => rxcelldataout,
    rbe         => rxCellempty,
    wbf         => rxwbf
  );  

  U3 : TranslateToUTOPIA 
  generic map(
    fifo_width  => fifo_width,
    Pclass      => Pclass,
    clock_syn   => clock_syn
  )
  Port map(
    reset       => reset,
    txclk       => utopia_clk,      
    sysclk      => sysclk,
    txaddr      => txaddr,
    txenb       => txenb,
    txclav      => txclav,
    txclaven    => txclaven, 
    txdata      => txdata,
    txdataen    => txdataen,
    txsoc       => txsoc,
    txsocen     => txsocen,
    rbe         => txbufempty,
    rdd         => txdataout,
    rdeop       => txrdeoc,
    rden        => txrden,
    rdport      => txrdport,
    timerset    => timerset,
    phyaddr     => phyaddr
  );

  rxrdd(fifo_width + status_bit - 1 downto fifo_width)  <= (others=>'0');
  
  U4 : ReceiveFromUTOPIA 
   generic map(
    fifo_width => fifo_width,
    clock_syn  => clock_syn
   )
   Port map (
    rxclk      => utopia_clk,
    sysclk     => sysclk,
    reset      => reset,
    rxdata     => rxdata,
    rxenb      => rxenb,
    rxsoc      => rxsoc,
    rxclav     => rxclav,
    rxclaven   => rxclaven,
    rxaddr     => rxaddr,
    wrd        => rxrdd(fifo_width - 1 downto 0),
    wren       => rxwren,
    wreop      => rxwreoc,
    wbf        => rxwbf,
    phyaddr    => phyaddr,
    cha        => cha
  );
   
end Behavioral;