dled.tan.summary

VHDL语言

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.327 ns
From           : scan_led:inst|dig_r[7]
To             : dig[7]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 178.89 MHz ( period = 5.590 ns )
From           : int_div:inst1|Counter[9]
To             : int_div:inst1|Temp2
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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