dled.map.rpt

VHDL语言

;     -- Combinational with no register       ; 33                     ;
;     -- Register only                        ; 9                      ;
;     -- Combinational with a register        ; 20                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 16                     ;
;     -- 3 input functions                    ; 9                      ;
;     -- 2 input functions                    ; 26                     ;
;     -- 1 input functions                    ; 2                      ;
;     -- 0 input functions                    ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 47                     ;
;     -- arithmetic mode                      ; 15                     ;
;     -- qfbk mode                            ; 0                      ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 0                      ;
;     -- asynchronous clear/load mode         ; 0                      ;
;                                             ;                        ;
; Total registers                             ; 29                     ;
; Total logic cells in carry chains           ; 16                     ;
; I/O pins                                    ; 17                     ;
; Maximum fan-out node                        ; scan_led:inst|count[0] ;
; Maximum fan-out                             ; 18                     ;
; Total fan-out                               ; 198                    ;
; Average fan-out                             ; 2.51                   ;
+---------------------------------------------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |dled                      ; 62 (0)      ; 29           ; 0           ; 17   ; 0            ; 33 (0)       ; 9 (0)             ; 20 (0)           ; 16 (0)          ; 0 (0)      ; |dled               ; work         ;
;    |int_div:inst1|         ; 44 (44)     ; 18           ; 0           ; 0    ; 0            ; 26 (26)      ; 9 (9)             ; 9 (9)            ; 16 (16)         ; 0 (0)      ; |dled|int_div:inst1 ; work         ;
;    |scan_led:inst|         ; 18 (18)     ; 11           ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 11 (11)          ; 0 (0)           ; 0 (0)      ; |dled|scan_led:inst ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------+
; Registers Removed During Synthesis                                   ;
+---------------------------------------+------------------------------+
; Register name                         ; Reason for Removal           ;
+---------------------------------------+------------------------------+
; inst/disp_dat[0]                      ; Merged with inst/count[0]    ;
; inst/disp_dat[3]                      ; Merged with inst/dig_r[0]    ;
; inst/count[1]                         ; Merged with inst/disp_dat[1] ;
; inst/count[2]                         ; Merged with inst/disp_dat[2] ;
; Total Number of Removed Registers = 4 ;                              ;
+---------------------------------------+------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_div:inst1 ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type                              ;
+----------------+-------+-----------------------------------+
; n              ; 48000 ; Untyped                           ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: 8constant:inst2|lpm_constant:lpm_constant_component ;
+--------------------+------------------+----------------------------------------------------------+
; Parameter Name     ; Value            ; Type                                                     ;
+--------------------+------------------+----------------------------------------------------------+
; LPM_WIDTH          ; 32               ; Untyped                                                  ;
; LPM_CVALUE         ; 305419896        ; Untyped                                                  ;
; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                  ;
; CBXI_PARAMETER     ; lpm_constant_br6 ; Untyped                                                  ;
+--------------------+------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Dec 01 11:23:51 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dled -c dled
Info: Found 2 design units, including 1 entities, in source file scan_led.vhd
    Info: Found design unit 1: scan_led-one
    Info: Found entity 1: scan_led
Info: Found 2 design units, including 1 entities, in source file int_div.vhd
    Info: Found design unit 1: int_div-Devider
    Info: Found entity 1: int_div
Info: Found 1 design units, including 1 entities, in source file dled.bdf
    Info: Found entity 1: dled
Info: Elaborating entity "dled" for the top level hierarchy
Info: Elaborating entity "scan_led" for hierarchy "scan_led:inst"
Info: Elaborating entity "int_div" for hierarchy "int_div:inst1"
Warning: Using design file 8constant.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: 8constant
Info: Elaborating entity "8constant" for hierarchy "8constant:inst2"
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2_7_1/quartus/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Elaborating entity "lpm_constant" for hierarchy "8constant:inst2|lpm_constant:lpm_constant_component"
Info: Elaborated megafunction instantiation "8constant:inst2|lpm_constant:lpm_constant_component"
Info: Found 1 design units, including 1 entities, in source file db/lpm_constant_br6.tdf
    Info: Found entity 1: lpm_constant_br6
Info: Elaborating entity "lpm_constant_br6" for hierarchy "8constant:inst2|lpm_constant:lpm_constant_component|lpm_constant_br6:ag"
Info: Duplicate registers merged to single register
    Info: Duplicate register "scan_led:inst|disp_dat[0]" merged to single register "scan_led:inst|count[0]"
    Info: Duplicate register "scan_led:inst|disp_dat[3]" merged to single register "scan_led:inst|dig_r[0]", power-up level changed
Info: Duplicate registers merged to single register
    Info: Duplicate register "scan_led:inst|count[1]" merged to single register "scan_led:inst|disp_dat[1]"
    Info: Duplicate register "scan_led:inst|count[2]" merged to single register "scan_led:inst|disp_dat[2]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg[7]" stuck at VCC
Info: Implemented 79 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 16 output pins
    Info: Implemented 62 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 155 megabytes of memory during processing
    Info: Processing ended: Mon Dec 01 11:24:12 2008
    Info: Elapsed time: 00:00:21