rom.tan.rpt

基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM）

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[4]                                                                                    ; count:u0|countt[4]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[5]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; clock      ; clock    ; None                        ; None                      ; 0.461 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[3]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; clock      ; clock    ; None                        ; None                      ; 0.452 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[4]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; clock      ; clock    ; None                        ; None                      ; 0.449 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[2]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; clock      ; clock    ; None                        ; None                      ; 0.447 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[0]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.488 ns                ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                  ;
+-------+--------------+------------+------------------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                         ; To   ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 5.683 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1] ; q[1] ; clock      ;
; N/A   ; None         ; 5.658 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5] ; q[5] ; clock      ;
; N/A   ; None         ; 5.331 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3] ; q[3] ; clock      ;
; N/A   ; None         ; 5.305 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2] ; q[2] ; clock      ;
; N/A   ; None         ; 5.300 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7] ; q[7] ; clock      ;
; N/A   ; None         ; 5.290 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0] ; q[0] ; clock      ;
; N/A   ; None         ; 5.287 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4] ; q[4] ; clock      ;
; N/A   ; None         ; 5.271 ns   ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6] ; q[6] ; clock      ;
+-------+--------------+------------+------------------------------------------------------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 01 15:49:50 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off rom -c rom --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 500.0 MHz between source memory "sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0" and destination memory "sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (1.0 ns) plus Clock Low delay (1.0 ns) : restricted to 2.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 1.720 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X16_Y8; Fanout = 8; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(1.720 ns) = 1.720 ns; Loc. = M512_X16_Y8; Fanout = 1; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]'
            Info: Total cell delay = 1.720 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.045 ns
            Info: + Shortest clock path from clock "clock" to destination memory is 2.252 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.642 ns) + CELL(0.413 ns) = 2.252 ns; Loc. = M512_X16_Y8; Fanout = 1; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]'
                Info: Total cell delay = 1.267 ns ( 56.26 % )
                Info: Total interconnect delay = 0.985 ns ( 43.74 % )
            Info: - Longest clock path from clock "clock" to source memory is 2.297 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.642 ns) + CELL(0.458 ns) = 2.297 ns; Loc. = M512_X16_Y8; Fanout = 8; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0'
                Info: Total cell delay = 1.312 ns ( 57.12 % )
                Info: Total interconnect delay = 0.985 ns ( 42.88 % )
        Info: + Micro clock to output delay of source is 0.140 ns
        Info: + Micro setup delay of destination is 0.022 ns
Info: tco from clock "clock" to destination pin "q[1]" through memory "sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]" is 5.683 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.252 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.642 ns) + CELL(0.413 ns) = 2.252 ns; Loc. = M512_X16_Y8; Fanout = 1; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]'
        Info: Total cell delay = 1.267 ns ( 56.26 % )
        Info: Total interconnect delay = 0.985 ns ( 43.74 % )
    Info: + Micro clock to output delay of source is 0.140 ns
    Info: + Longest memory to pin delay is 3.291 ns
        Info: 1: + IC(0.000 ns) + CELL(0.065 ns) = 0.065 ns; Loc. = M512_X16_Y8; Fanout = 1; MEM Node = 'sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]'
        Info: 2: + IC(1.072 ns) + CELL(2.154 ns) = 3.291 ns; Loc. = PIN_R21; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 2.219 ns ( 67.43 % )
        Info: Total interconnect delay = 1.072 ns ( 32.57 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Thu Jan 01 15:49:51 2009
    Info: Elapsed time: 00:00:01