rom.tan.rpt

基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM）

; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                               ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                  ; To                                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[0]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[1]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[2]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[3]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg0 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg2 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg3 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg4 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.845 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[4]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.810 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[3]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.775 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; count:u0|countt[4]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[2]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[2]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.740 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; count:u0|countt[3]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[2]                                                                                    ; count:u0|countt[4]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[3]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[5]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg5 ; clock      ; clock    ; None                        ; None                      ; 0.620 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; sin:u1|altsyncram:altsyncram_component|altsyncram_tc71:auto_generated|ram_block1a0~porta_address_reg1 ; clock      ; clock    ; None                        ; None                      ; 0.614 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; count:u0|countt[2]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[2]                                                                                    ; count:u0|countt[3]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[3]                                                                                    ; count:u0|countt[4]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[4]                                                                                    ; count:u0|countt[5]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[0]                                                                                    ; count:u0|countt[1]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.677 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[1]                                                                                    ; count:u0|countt[1]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[2]                                                                                    ; count:u0|countt[2]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count:u0|countt[3]                                                                                    ; count:u0|countt[3]                                                                                    ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;