rom.vhd.bak

来自「基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM）」· BAK 代码 · 共 24 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sinx is 
port(   
		q		    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		clock		: IN STD_LOGIC );
end sinx;
architecture rtl of sinx is
component count
   port(address		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
        clock		: IN STD_LOGIC ); 
   end component;
component sin
   port(address		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
   end component;
signal  address	: STD_LOGIC_VECTOR (5 DOWNTO 0);
begin
   u0: count port map( clock=>clock, address=>address);
   u1: sin port map( clock=>clock,address=>address, q=>q);
end rtl;