prev_cmp_mips_top.fit.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:11 " "Info: Fitter routing operations ending: elapsed time is 00:00:11" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_POST_FIT_LOGIC_DUPLICATION" "2 " "Info: Duplicated 2 combinational logic cells to improve design speed or routability" {  } {  } 0 0 "Duplicated %1!d! combinational logic cells to improve design speed or routability" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_POST_FIT_REGISTER_DUPLICATION" "4 " "Info: Duplicated 4 registered logic cells to improve design speed or routability" {  } {  } 0 0 "Duplicated %1!d! registered logic cells to improve design speed or routability" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "32 " "Warning: Found 32 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "instruction\[0\] 0 " "Info: Pin \"instruction\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "instruction\[1\] 0 " "Info: Pin \"instruction\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of