mips_top.hier_info

是verilog做的简化mips32指令系统。 有些小问题

next_pc[16] <= next_pc[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[17] <= next_pc[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[18] <= next_pc[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[19] <= next_pc[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[20] <= next_pc[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[21] <= next_pc[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[22] <= next_pc[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[23] <= next_pc[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[24] <= next_pc[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[25] <= next_pc[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[26] <= next_pc[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[27] <= next_pc[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[28] <= next_pc[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[29] <= next_pc[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[30] <= next_pc[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
next_pc[31] <= next_pc[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[31].OE
memenab => otri[30].OE
memenab => otri[29].OE
memenab => otri[28].OE
memenab => otri[27].OE
memenab => otri[26].OE
memenab => otri[25].OE
memenab => otri[24].OE
memenab => otri[23].OE
memenab => otri[22].OE
memenab => otri[21].OE
memenab => otri[20].OE
memenab => otri[19].OE
memenab => otri[18].OE
memenab => otri[17].OE
memenab => otri[16].OE
memenab => otri[15].OE
memenab => otri[14].OE
memenab => otri[13].OE
memenab => otri[12].OE
memenab => otri[11].OE
memenab => otri[10].OE
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= otri[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= otri[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= otri[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= otri[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= otri[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= otri[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= otri[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= otri[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= otri[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= otri[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= otri[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= otri[27].DB_MAX_OUTPUT_PORT_TYPE
q[28] <= otri[28].DB_MAX_OUTPUT_PORT_TYPE
q[29] <= otri[29].DB_MAX_OUTPUT_PORT_TYPE
q[30] <= otri[30].DB_MAX_OUTPUT_PORT_TYPE
q[31] <= otri[31].DB_MAX_OUTPUT_PORT_TYPE


|Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
address[8] => altsyncram:rom_block.address_a[8]
address[9] => altsyncram:rom_block.address_a[9]
clocki => altsyncram:rom_block.clock0
clocko => altsyncram:rom_block.clock1
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= altsyncram:rom_block.q_a[9]
q[10] <= altsyncram:rom_block.q_a[10]
q[11] <= altsyncram:rom_block.q_a[11]
q[12] <= altsyncram:rom_block.q_a[12]
q[13] <= altsyncram:rom_block.q_a[13]
q[14] <= altsyncram:rom_block.q_a[14]
q[15] <= altsyncram:rom_block.q_a[15]
q[16] <= altsyncram:rom_block.q_a[16]
q[17] <= altsyncram:rom_block.q_a[17]
q[18] <= altsyncram:rom_block.q_a[18]
q[19] <= altsyncram:rom_block.q_a[19]
q[20] <= altsyncram:rom_block.q_a[20]
q[21] <= altsyncram:rom_block.q_a[21]
q[22] <= altsyncram:rom_block.q_a[22]
q[23] <= altsyncram:rom_block.q_a[23]
q[24] <= altsyncram:rom_block.q_a[24]
q[25] <= altsyncram:rom_block.q_a[25]
q[26] <= altsyncram:rom_block.q_a[26]
q[27] <= altsyncram:rom_block.q_a[27]
q[28] <= altsyncram:rom_block.q_a[28]
q[29] <= altsyncram:rom_block.q_a[29]
q[30] <= altsyncram:rom_block.q_a[30]
q[31] <= altsyncram:rom_block.q_a[31]


|Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_7201:auto_generated.address_a[0]
address_a[1] => altsyncram_7201:auto_generated.address_a[1]
address_a[2] => altsyncram_7201:auto_generated.address_a[2]
address_a[3] => altsyncram_7201:auto_generated.address_a[3]
address_a[4] => altsyncram_7201:auto_generated.address_a[4]
address_a[5] => altsyncram_7201:auto_generated.address_a[5]
address_a[6] => altsyncram_7201:auto_generated.address_a[6]
address_a[7] => altsyncram_7201:auto_generated.address_a[7]
address_a[8] => altsyncram_7201:auto_generated.address_a[8]
address_a[9] => altsyncram_7201:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_7201:auto_generated.clock0
clock1 => altsyncram_7201:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_7201:auto_generated.q_a[0]
q_a[1] <= altsyncram_7201:auto_generated.q_a[1]
q_a[2] <= altsyncram_7201:auto_generated.q_a[2]
q_a[3] <= altsyncram_7201:auto_generated.q_a[3]
q_a[4] <= altsyncram_7201:auto_generated.q_a[4]
q_a[5] <= altsyncram_7201:auto_generated.q_a[5]
q_a[6] <= altsyncram_7201:auto_generated.q_a[6]
q_a[7] <= altsyncram_7201:auto_generated.q_a[7]
q_a[8] <= altsyncram_7201:auto_generated.q_a[8]
q_a[9] <= altsyncram_7201:auto_generated.q_a[9]
q_a[10] <= altsyncram_7201:auto_generated.q_a[10]
q_a[11] <= altsyncram_7201:auto_generated.q_a[11]
q_a[12] <= altsyncram_7201:auto_generated.q_a[12]
q_a[13] <= altsyncram_7201:auto_generated.q_a[13]
q_a[14] <= altsyncram_7201:auto_generated.q_a[14]
q_a[15] <= altsyncram_7201:auto_generated.q_a[15]
q_a[16] <= altsyncram_7201:auto_generated.q_a[16]
q_a[17] <= altsyncram_7201:auto_generated.q_a[17]
q_a[18] <= altsyncram_7201:auto_generated.q_a[18]
q_a[19] <= altsyncram_7201:auto_generated.q_a[19]
q_a[20] <= altsyncram_7201:auto_generated.q_a[20]
q_a[21] <= altsyncram_7201:auto_generated.q_a[21]
q_a[22] <= altsyncram_7201:auto_generated.q_a[22]
q_a[23] <= altsyncram_7201:auto_generated.q_a[23]
q_a[24] <= altsyncram_7201:auto_generated.q_a[24]
q_a[25] <= altsyncram_7201:auto_generated.q_a[25]
q_a[26] <= altsyncram_7201:auto_generated.q_a[26]
q_a[27] <= altsyncram_7201:auto_generated.q_a[27]
q_a[28] <= altsyncram_7201:auto_generated.q_a[28]
q_a[29] <= altsyncram_7201:auto_generated.q_a[29]
q_a[30] <= altsyncram_7201:auto_generated.q_a[30]
q_a[31] <= altsyncram_7201:auto_generated.q_a[31]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3