prev_cmp_mips_top.map.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 17 23:23:37 2008 " "Info: Processing started: Wed Dec 17 23:23:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mips_Top -c Mips_Top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Mips_Top -c Mips_Top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "clock_gen.v(13) " "Warning (10268): Verilog HDL information at clock_gen.v(13): Always Construct contains both blocking and non-blocking assignments" {  } { { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 13 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_gen " "Info: Found entity 1: clock_gen" {  } { { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add32.v" { { "Info" "ISGN_ENTITY_NAME" "1 add32 " "Info: Found entity 1: add32" {  } { { "add32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/add32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALU32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU32 " "Info: Found entity 1: ALU32" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALUDecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALUDecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALUDecoder " "Info: Found entity 1: ALUDecoder" {  } { { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Controler.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Controler.v" { { "Info" "ISGN_ENTITY_NAME" "1 Controler " "Info: Found entity 1: Controler" {  } { { "Controler.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Controler.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dmemory32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Dmemory32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Dmemory32 " "Info: Found entity 1: Dmemory32" {  } { { "Dmemory32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Dmemory32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Ifetch32.v(29) " "Warning (10268): Verilog HDL information at Ifetch32.v(29): Always Construct contains both blocking and non-blocking assignments" {  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 29 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ifetch32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Ifetch32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Ifetch32 " "Info: Found entity 1: Ifetch32" {  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Registers32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Registers32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Registers32 " "Info: Found entity 1: Registers32" {  } { { "Registers32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Registers32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter32_var.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter32_var.v" { { "Info" "ISGN_ENTITY_NAME" "1 shifter32_var " "Info: Found entity 1: shifter32_var" {  } { { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SignExt32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SignExt32.v" { { "Info" "ISGN_ENTITY_NAME" "1 SignExt32 " "Info: Found entity 1: SignExt32" {  } { { "SignExt32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/SignExt32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "Mips_Top.v(42) " "Warning (10275): Verilog HDL Module Instantiation warning at Mips_Top.v(42): ignored dangling comma in List of Port Connections" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 42 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "Mips_Top.v(83) " "Warning (10275): Verilog HDL Module Instantiation warning at Mips_Top.v(83): ignored dangling comma in List of Port Connections" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 83 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "rwds Mips_Top.v(53) " "Warning (10236): Verilog HDL Implicit Net warning at Mips_Top.v(53): created implicit net for \"rwds\"" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 53 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mips_Top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Mips_Top.v" { { "Info" "ISGN_ENTITY_NAME" "1 Mips_Top " "Info: Found entity 1: Mips_Top" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "c0 ALU32.v(34) " "Error (10137): Verilog HDL Procedural Assignment error at ALU32.v(34): object \"c0\" on left-hand side of assignment must have a variable data type" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 34 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.map.smsg " "Info: Generated suppressed messages file D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  2 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "147 " "Info: Allocated 147 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Dec 17 23:23:40 2008 " "Error: Processing ended: Wed Dec 17 23:23:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}