mips_top.tan.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register ALU32:alu\|s1\[19\] register ALU32:alu\|shifter32_var:myshift\|outreg\[3\] 76.27 MHz 13.112 ns Internal " "Info: Clock \"clock\" has Internal fmax of 76.27 MHz between source register \"ALU32:alu\|s1\[19\]\" and destination register \"ALU32:alu\|shifter32_var:myshift\|outreg\[3\]\" (period= 13.112 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.378 ns + Longest register register " "Info: + Longest register to register delay is 6.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ALU32:alu\|s1\[19\] 1 REG LCCOMB_X29_Y4_N30 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X29_Y4_N30; Fanout = 32; REG Node = 'ALU32:alu\|s1\[19\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ALU32:alu|s1[19] } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.221 ns) + CELL(0.228 ns) 2.449 ns ALU32:alu\|shifter32_var:myshift\|outreg~14130 2 COMB LCCOMB_X10_Y9_N8 1 " "Info: 2: + IC(2.221 ns) + CELL(0.228 ns) = 2.449 ns; Loc. = LCCOMB_X10_Y9_N8; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14130'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { ALU32:alu|s1[19] ALU32:alu|shifter32_var:myshift|outreg~14130 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.228 ns) 3.737 ns ALU32:alu\|shifter32_var:myshift\|outreg~14131 3 COMB LCCOMB_X15_Y6_N8 1 " "Info: 3: + IC(1.060 ns) + CELL(0.228 ns) = 3.737 ns; Loc. = LCCOMB_X15_Y6_N8; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14131'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { ALU32:alu|shifter32_var:myshift|outreg~14130 ALU32:alu|shifter32_var:myshift|outreg~14131 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.049 ns) + CELL(0.228 ns) 5.014 ns ALU32:alu\|shifter32_var:myshift\|outreg~14132 4 COMB LCCOMB_X22_Y4_N2 1 " "Info: 4: + IC(1.049 ns) + CELL(0.228 ns) = 5.014 ns; Loc. = LCCOMB_X22_Y4_N2; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14132'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { ALU32:alu|shifter32_var:myshift|outreg~14131 ALU32:alu|shifter32_var:myshift|outreg~14132 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.154 ns) 6.223 ns ALU32:alu\|shifter32_var:myshift\|outreg~14140 5 COMB LCCOMB_X15_Y7_N2 1 " "Info: 5: + IC(1.055 ns) + CELL(0.154 ns) = 6.223 ns; Loc. = LCCOMB_X15_Y7_N2; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14140'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.209 ns" { ALU32:alu|shifter32_var:myshift|outreg~14132 ALU32:alu|shifter32_var:myshift|outreg~14140 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 6.378 ns ALU32:alu\|shifter32_var:myshift\|outreg\[3\] 6 REG LCFF_X15_Y7_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 6.378 ns; Loc. = LCFF_X15_Y7_N3; Fanout = 1; REG Node = 'ALU32:alu\|shifter32_var:myshift\|outreg\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { ALU32:alu|shifter32_var:myshift|outreg~14140 ALU32:alu|shifter32_var:myshift|outreg[3] } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.993 ns ( 15.57 % ) " "Info: Total cell delay = 0.993 ns ( 15.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.385 ns ( 84.43 % ) " "Info: Total interconnect delay = 5.385 ns ( 84.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.378 ns" { ALU32:alu|s1[19] ALU32:alu|shifter32_var:myshift|outreg~14130 ALU32:alu|shifter32_var:myshift|outreg~14131 ALU32:alu|shifter32_var:myshift|outreg~14132 ALU32:alu|shifter32_var:myshift|outreg~14140 ALU32:alu|shifter32_var:myshift|outreg[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.378 ns" { ALU32:alu|s1[19] {} ALU32:alu|shifter32_var:myshift|outreg~14130 {} ALU32:alu|shifter32_var:myshift|outreg~14131 {} ALU32:alu|shifter32_var:myshift|outreg~14132 {} ALU32:alu|shifter32_var:myshift|outreg~14140 {} ALU32:alu|shifter32_var:myshift|outreg[3] {} } { 0.000ns 2.221ns 1.060ns 1.049ns 1.055ns 0.000ns } { 0.000ns 0.228ns 0.228ns 0.228ns 0.154ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.088 ns - Smallest " "Info: - Smallest clock skew is -0.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 8.624 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 8.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 6 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 6; CLK Node = 'clock'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.712 ns) 3.233 ns clock_gen:clocks\|aludecoderclk 2 REG LCFF_X39_Y11_N1 5 " "Info: 2: + IC(1.667 ns) + CELL(0.712 ns) = 3.233 ns; Loc. = LCFF_X39_Y11_N1; Fanout = 5; REG Node = 'clock_gen:clocks\|aludecoderclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.379 ns" { clock clock_gen:clocks|aludecoderclk } "NODE_NAME" } } { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.712 ns) 5.253 ns ALUDecoder:aludecoder\|aluctrl\[3\] 3 REG LCFF_X19_Y8_N5 7 " "Info: 3: + IC(1.308 ns) + CELL(0.712 ns) = 5.253 ns; Loc. = LCFF_X19_Y8_N5; Fanout = 7; REG Node = 'ALUDecoder:aludecoder\|aluctrl\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.020 ns" { clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[3] } "NODE_NAME" } } { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.234 ns) + CELL(0.053 ns) 5.540 ns ALU32:alu\|shclk 4 COMB LCCOMB_X19_Y8_N20 2 " "Info: 4: + IC(0.234 ns) + CELL(0.053 ns) = 5.540 ns; Loc. = LCCOMB_X19_Y8_N20; Fanout = 2; COMB Node = 'ALU32:alu\|shclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.287 ns" { ALUDecoder:aludecoder|aluctrl[3] ALU32:alu|shclk } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.830 ns) + CELL(0.000 ns) 7.370 ns ALU32:alu\|shclk~clkctrl 5 COMB CLKCTRL_G2 70 " "Info: 5: + IC(1.830 ns) + CELL(0.000 ns) = 7.370 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'ALU32:alu\|shclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.830 ns" { ALU32:alu|shclk ALU32:alu|shclk~clkctrl } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.618 ns) 8.624 ns ALU32:alu\|shifter32_var:myshift\|outreg\[3\] 6 REG LCFF_X15_Y7_N3 1 " "Info: 6: + IC(0.636 ns) + CELL(0.618 ns) = 8.624 ns; Loc. = LCFF_X15_Y7_N3; Fanout = 1; REG Node = 'ALU32:alu\|shifter32_var:myshift\|outreg\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.254 ns" { ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[3] } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.949 ns ( 34.20 % ) " "Info: Total cell delay = 2.949 ns ( 34.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.675 ns ( 65.80 % ) " "Info: Total interconnect delay = 5.675 ns ( 65.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.624 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[3] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.624 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[3] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|shifter32_var:myshift|outreg[3] {} } { 0.000ns 0.000ns 1.667ns 1.308ns 0.234ns 1.830ns 0.636ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 8.712 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 8.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 6 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 6; CLK Node = 'clock'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.712 ns) 3.233 ns clock_gen:clocks\|aludecoderclk 2 REG LCFF_X39_Y11_N1 5 " "Info: 2: + IC(1.667 ns) + CELL(0.712 ns) = 3.233 ns; Loc. = LCFF_X39_Y11_N1; Fanout = 5; REG Node = 'clock_gen:clocks\|aludecoderclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.379 ns" { clock clock_gen:clocks|aludecoderclk } "NODE_NAME" } } { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.712 ns) 5.253 ns ALUDecoder:aludecoder\|aluctrl\[2\] 3 REG LCFF_X19_Y8_N9 73 " "Info: 3: + IC(1.308 ns) + CELL(0.712 ns) = 5.253 ns; Loc. = LCFF_X19_Y8_N9; Fanout = 73; REG Node = 'ALUDecoder:aludecoder\|aluctrl\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.020 ns" { clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] } "NODE_NAME" } } { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.228 ns) 5.750 ns ALU32:alu\|shclk 4 COMB LCCOMB_X19_Y8_N20 2 " "Info: 4: + IC(0.269 ns) + CELL(0.228 ns) = 5.750 ns; Loc. = LCCOMB_X19_Y8_N20; Fanout = 2; COMB Node = 'ALU32:alu\|shclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.497 ns" { ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.830 ns) + CELL(0.000 ns) 7.580 ns ALU32:alu\|shclk~clkctrl 5 COMB CLKCTRL_G2 70 " "Info: 5: + IC(1.830 ns) + CELL(0.000 ns) = 7.580 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'ALU32:alu\|shclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.830 ns" { ALU32:alu|shclk ALU32:alu|shclk~clkctrl } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.225 ns) 8.712 ns ALU32:alu\|s1\[19\] 6 REG LCCOMB_X29_Y4_N30 32 " "Info: 6: + IC(0.907 ns) + CELL(0.225 ns) = 8.712 ns; Loc. = LCCOMB_X29_Y4_N30; Fanout = 32; REG Node = 'ALU32:alu\|s1\[19\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { ALU32:alu|shclk~clkctrl ALU32:alu|s1[19] } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.731 ns ( 31.35 % ) " "Info: Total cell delay = 2.731 ns ( 31.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.981 ns ( 68.65 % ) " "Info: Total interconnect delay = 5.981 ns ( 68.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.712 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|s1[19] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.712 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[2] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|s1[19] {} } { 0.000ns 0.000ns 1.667ns 1.308ns 0.269ns 1.830ns 0.907ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.228ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.624 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[3] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.624 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[3] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|shifter32_var:myshift|outreg[3] {} } { 0.000ns 0.000ns 1.667ns 1.308ns 0.234ns 1.830ns 0.636ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.053ns 0.000ns 0.618ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.712 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|s1[19] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.712 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[2] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|s1[19] {} } { 0.000ns 0.000ns 1.667ns 1.308ns 0.269ns 1.830ns 0.907ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.228ns 0.000ns 0.225ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { {