📄 mips_top.map.rpt
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; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; clock_gen.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v ;
; add32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/add32.v ;
; ALU32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v ;
; ALUDecoder.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v ;
; Controler.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Controler.v ;
; Dmemory32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Dmemory32.v ;
; Ifetch32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v ;
; Registers32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Registers32.v ;
; shifter32_var.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v ;
; SignExt32.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/SignExt32.v ;
; Mips_Top.v ; yes ; User Verilog HDL File ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v ;
; lpm_rom.tdf ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf ;
; altrom.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altrom.inc ;
; aglobal72.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/aglobal72.inc ;
; altrom.tdf ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altrom.tdf ;
; memmodes.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/others/maxplus2/memmodes.inc ;
; lpm_decode.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_mux.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc ;
; altqpram.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altqpram.inc ;
; altsyncram.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altsyncram.inc ;
; altsyncram.tdf ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altram.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; e:/altera/72/quartus/libraries/megafunctions/altdpram.inc ;
; db/altsyncram_7201.tdf ; yes ; Auto-Generated Megafunction ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/db/altsyncram_7201.tdf ;
; db/altsyncram_bkf1.tdf ; yes ; Auto-Generated Megafunction ; D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/db/altsyncram_bkf1.tdf ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------------------+-----------------------------+
; Resource ; Usage ;
+-----------------------------------------------+-----------------------------+
; Estimated ALUTs Used ; 2680 ;
; Dedicated logic registers ; 2872 ;
; ; ;
; Estimated ALUTs Unavailable ; 1111 ;
; ; ;
; Total combinational functions ; 2680 ;
; Combinational ALUT usage by number of inputs ; ;
; -- 7 input functions ; 1 ;
; -- 6 input functions ; 1268 ;
; -- 5 input functions ; 505 ;
; -- 4 input functions ; 429 ;
; -- <=3 input functions ; 477 ;
; ; ;
; Combinational ALUTs by mode ; ;
; -- normal mode ; 2567 ;
; -- extended LUT mode ; 1 ;
; -- arithmetic mode ; 112 ;
; -- shared arithmetic mode ; 0 ;
; ; ;
; Estimated ALUT/register pairs used ; 3791 ;
; ; ;
; Total registers ; 2872 ;
; -- Dedicated logic registers ; 2872 ;
; -- I/O registers ; 0 ;
; ; ;
; Estimated ALMs: partially or completely used ; 1,896 ;
; ; ;
; I/O pins ; 34 ;
; Total block memory bits ; 33280 ;
; Maximum fan-out node ; clock_gen:clocks|dmemoryclk ;
; Maximum fan-out ; 1569 ;
; Total fan-out ; 25993 ;
; Average fan-out ; 4.62 ;
+-----------------------------------------------+-----------------------------+
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