mips_top.map.rpt

是verilog做的简化mips32指令系统。 有些小问题

Analysis & Synthesis report for Mips_Top
Wed Dec 17 23:25:32 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |Mips_Top|clock_gen:clocks|state
  9. User-Specified and Inferred Latches
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated
 14. Source assignments for Dmemory32:dmemory|altsyncram:dmemory32[0][7]__1|altsyncram_bkf1:auto_generated
 15. Parameter Settings for User Entity Instance: clock_gen:clocks
 16. Parameter Settings for User Entity Instance: Ifetch32:ifetch|lpm_rom:prgrom
 17. Parameter Settings for User Entity Instance: Dmemory32:dmemory|altsyncram:dmemory32[0][7]__1
 18. Analysis & Synthesis Messages
 19. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                             ;
+-------------------------------+------------------------------------------+
; Analysis & Synthesis Status   ; Successful - Wed Dec 17 23:25:32 2008    ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                 ; Mips_Top                                 ;
; Top-level Entity Name         ; Mips_Top                                 ;
; Family                        ; Stratix II                               ;
; Logic utilization             ; N/A                                      ;
;     Combinational ALUTs       ; 2,680                                    ;
;     Dedicated logic registers ; 2,872                                    ;
; Total registers               ; 2872                                     ;
; Total pins                    ; 34                                       ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 33,280                                   ;
; DSP block 9-bit elements      ; 0                                        ;
; Total PLLs                    ; 0                                        ;
; Total DLLs                    ; 0                                        ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                         ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                      ; Setting            ; Default Value      ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                       ; Mips_Top           ; Mips_Top           ;
; Family name                                                                 ; Stratix II         ; Stratix II         ;
; Use Generated Physical Constraints File                                     ; Off                ;                    ;
; Use smart compilation                                                       ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                         ; 1                  ; 1                  ;
; Restructure Multiplexers                                                    ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                         ; Off                ; Off                ;
; Preserve fewer node names                                                   ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                   ; Off                ; Off                ;
; Verilog Version                                                             ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                    ; Auto               ; Auto               ;
; Safe State Machine                                                          ; Off                ; Off                ;
; Extract Verilog State Machines                                              ; On                 ; On                 ;
; Extract VHDL State Machines                                                 ; On                 ; On                 ;
; Ignore Verilog initial constructs                                           ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                     ; On                 ; On                 ;
; Parallel Synthesis                                                          ; Off                ; Off                ;
; DSP Block Balancing                                                         ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                          ; On                 ; On                 ;
; Power-Up Don't Care                                                         ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                ; Off                ; Off                ;
; Remove Duplicate Registers                                                  ; On                 ; On                 ;
; Ignore CARRY Buffers                                                        ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                      ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                   ; Off                ; Off                ;
; Ignore LCELL Buffers                                                        ; Off                ; Off                ;
; Ignore SOFT Buffers                                                         ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                              ; Off                ; Off                ;
; Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix II/Stratix III                                ; 70                 ; 70                 ;