clock_gen.v

是verilog做的简化mips32指令系统。 有些小问题

module clock_gen (clock,reset,registersclk,controlerclk,dmemoryclk,ifetchclk,aludecoderclk,aluclk,sigextclk); 
input clock,reset; 
output reg registersclk,controlerclk,dmemoryclk,ifetchclk,aludecoderclk,aluclk,sigextclk; 
reg[6:0] state; 
parameter	S1 = 8'b0000001, 
			S2 = 8'b0000010, 
			S3 = 8'b0000100, 
			S4 = 8'b0001000, 
			S5 = 8'b0010000, 
			S6 = 8'b0100000, 
			S7 = 8'b1000000, 
			idle = 8'b0000000;					
always @(posedge clock) 
	if(reset) 
	begin 
		registersclk=0;
		controlerclk=0;
		dmemoryclk=1;
		ifetchclk=0;
		aludecoderclk=0;
		aluclk=0;
		sigextclk=0;
		state <= idle; 
	end 
	else 
	begin  
		case(state) 
		S1: 
		begin 
			ifetchclk=~ifetchclk;  
			state <= S2; 
		end 
		S2: 
		begin 
			controlerclk=~controlerclk;
			sigextclk=~sigextclk;
			state <= S3; 
		end 
		S3: 
		begin	 
			controlerclk=~controlerclk;
			sigextclk=~sigextclk;
			aludecoderclk=~aludecoderclk;
			registersclk=~registersclk; 
			state <= S4; 
		end 
		S4: 
		begin 
			aludecoderclk=~aludecoderclk;
			aluclk=~aluclk; 
			state <= S5; 
		end 
		S5: 
		begin 
			dmemoryclk=~dmemoryclk; 
			state <= S6; 
		end 
		S6: 
		begin 
			registersclk=~registersclk;
			dmemoryclk=~dmemoryclk;
			aluclk=~aluclk; 
			state <= S7; 
		end 
		S7: 
		begin 
			ifetchclk=~ifetchclk;  
			state <=  S1; 
		end 
		idle:state <= S1;	 
		default:state <= idle;					 
		endcase 
	end 
endmodule