ifetch32.v.bak

是verilog做的简化mips32指令系统。 有些小问题

`timescale 100ps/1ps
module Ifetch32(AluZero,j,jr,ib,b,clk,reset,ReadData1,offset,instruction,pc_inc,next_pc);
	input AluZero;
	input j;
	input jr;
	input ib;
	input b;
	input clk;
	input reset;
	input [31:0] ReadData1;
	input [31:0] offset;
	output reg [31:0] instruction;
	wire [31:0] instructionwire;
	output reg [31:0] next_pc;
    output reg [31:0] pc_inc;
	reg [31:0] jumpaddr;
	reg [31:0] tmp1;
	reg [31:0] pc;
	wire tmpsig;

	lpm_rom prgrom(.address(pc[11:2]),.inclock(clk),.outclock(~clk),.q(instruction[31:0]));//use library lpm_rom from quartus
	defparam prgrom.lpm_width=32;
	defparam prgrom.lpm_widthad=10;//PC[31:12]=0,for the memory mustn't be too large
	defparam prgrom.lpm_file="mips32.mif";//instructions file
	defparam prgrom.lpm_outdata="REGISTERED";
	defparam prgrom.lpm_address_control="REGISTERED";

	assign	tmpsig=ib&((AluZero&b)^(!AluZero&!b));
	always @(negedge clk)
	begin
	   if(reset == 1'b1)
		   begin
		       pc <= 32'b0;
		       next_pc <= 32'b0;
		   end
		else
		   begin
		      pc = next_pc;
		      pc_inc = pc+1;//in our system , one instruction is in one address unit  
		      jumpaddr[31:0]={pc_inc[31:26],instruction[25:0]};//as above
		      tmp1=pc_inc+offset;
		      if(j == 1'b1)
		         begin
		            next_pc=jumpaddr;
		         end    
		      else if(jr ==1'b1)
		         begin
		             next_pc=ReadData1;
		         end
		      else 
		         begin
		             if(tmpsig == 1'b1)
		                begin
		                    next_pc=tmp1;
		                end
		             else
		                begin
		                    next_pc=pc_inc;
		                end      
			      end
			   
		end
	end
endmodule