controler.v

是verilog做的简化mips32指令系统。 有些小问题

module Controler(opcode,clk,rd,j,jr,ib,b,aluop,alusrc,rwds,rw,rwdw,mwdw,mr,mw,mtr);
	input[5:0] opcode;
	input clk;
	
	output reg [1:0] rd; //RegDest
	output reg j; //Jump
	output reg jr; //JumpReg
	output reg ib; //IsReanch
	output reg b; //Branch
	output reg [1:0] aluop; //ALUop
	output reg alusrc; //AluSrc
	output reg rwds; //RegWriteDataSrc
	output reg rw; //RegWrite
	output reg [1:0] rwdw; //RegWriteDataWidth
	output reg [1:0] mwdw; //MemWriteDataWidth
	output reg mr; //MemRead
	output reg mw; //MemWrite
	output reg mtr; //MemToReg
	
	always @ (posedge clk)
	begin
		rd[0]<= (!opcode[5]&!opcode[4]& opcode[3]&!opcode[2]& opcode[1]&!opcode[0])
			   |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]&!opcode[1]&!opcode[0])
			   |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]&!opcode[1]& opcode[0])
			   |(!opcode[5]&!opcode[4]& opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			   |( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			   |( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]& opcode[0])
			   |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]& opcode[1]& opcode[0])
			   |( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0])
			   |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
		rd[1]<= (!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			   |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
		
		j<= (!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0])
		   |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]&!opcode[0]);
		
		jr<= (!opcode[5]& opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0]);
		
		ib<= (!opcode[5]&!opcode[4]&!opcode[3]& opcode[2]&!opcode[1]&!opcode[0])
			|(!opcode[5]&!opcode[4]&!opcode[3]& opcode[2]&!opcode[1]& opcode[0]);
		
		b<= (!opcode[5]&!opcode[4]&!opcode[3]& opcode[2]&!opcode[1]&!opcode[0]);
		
		aluop[0]<= (!opcode[5]&!opcode[4]&!opcode[3]& opcode[2]&!opcode[1]&!opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]& opcode[2]&!opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]& opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]&!opcode[0])
				  |(!opcode[5]& opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0]);
		aluop[1]<= (!opcode[5]&!opcode[4]& opcode[3]&!opcode[2]& opcode[1]&!opcode[0])
				  |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]&!opcode[1]&!opcode[0])
				  |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]&!opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]& opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
				  |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]& opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0])
				  |(!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]&!opcode[0])
				  |(!opcode[5]& opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0]);
		
		alusrc<= ( opcode[5]| opcode[4]| opcode[3]|!opcode[2]| opcode[1]| opcode[0])
				&( opcode[5]| opcode[4]| opcode[3]|!opcode[2]| opcode[1]|!opcode[0])
				&( opcode[5]| opcode[4]| opcode[3]| opcode[2]| opcode[1]| opcode[0]);
		
		rwds<= (!opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
		
		rw<= ( opcode[5]| opcode[4]| opcode[3]| opcode[2]|!opcode[1]| opcode[0])
			&( opcode[5]| opcode[4]| opcode[3]|!opcode[2]| opcode[1]| opcode[0])
			&( opcode[5]| opcode[4]| opcode[3]|!opcode[2]| opcode[1]|!opcode[0])
			&( opcode[5]|!opcode[4]| opcode[3]| opcode[2]| opcode[1]| opcode[0])
			&(!opcode[5]| opcode[4]|!opcode[3]| opcode[2]| opcode[1]| opcode[0])
			&(!opcode[5]| opcode[4]|!opcode[3]| opcode[2]| opcode[1]|!opcode[0])
			&(!opcode[5]| opcode[4]|!opcode[3]| opcode[2]|!opcode[1]|!opcode[0]);
		
		rwdw[0]<= ( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]& opcode[0])
				 |(!opcode[5]&!opcode[4]& opcode[3]& opcode[2]& opcode[1]& opcode[0]);
		rwdw[1]<= (!opcode[5]| opcode[4]| opcode[3]| opcode[2]| opcode[1]| opcode[0])
				 &(!opcode[5]| opcode[4]| opcode[3]| opcode[2]| opcode[1]|!opcode[0]);
		
		mwdw[0]<= ( opcode[5]&!opcode[4]& opcode[3]&!opcode[2]&!opcode[1]& opcode[0]);
		mwdw[1]<= ( opcode[5]&!opcode[4]& opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
		
		mr<= ( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			|( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]& opcode[0])
			|( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
		
		mw<= ( opcode[5]&!opcode[4]& opcode[3]&!opcode[2]& opcode[1]& opcode[0])
			|( opcode[5]&!opcode[4]& opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			|( opcode[5]&!opcode[4]& opcode[3]&!opcode[2]&!opcode[1]& opcode[0]);
		
		mtr<= ( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]&!opcode[0])
			 |( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]&!opcode[1]& opcode[0])
			 |( opcode[5]&!opcode[4]&!opcode[3]&!opcode[2]& opcode[1]& opcode[0]);
	end	
	
endmodule