mips_top.sim.rpt

是verilog做的简化mips32指令系统。 有些小问题

; |Mips_Top|SignExt32:signext|offset[15]                                                                                 ; |Mips_Top|SignExt32:signext|offset[15]                                                                           ; regout           ;
; |Mips_Top|SignExt32:signext|offset[14]                                                                                 ; |Mips_Top|SignExt32:signext|offset[14]                                                                           ; regout           ;
; |Mips_Top|SignExt32:signext|offset[13]                                                                                 ; |Mips_Top|SignExt32:signext|offset[13]                                                                           ; regout           ;
; |Mips_Top|SignExt32:signext|offset[12]                                                                                 ; |Mips_Top|SignExt32:signext|offset[12]                                                                           ; regout           ;
; |Mips_Top|Controler:controler|aluop[1]                                                                                 ; |Mips_Top|Controler:controler|aluop[1]                                                                           ; regout           ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~613                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~613                                                                      ; combout          ;
; |Mips_Top|Registers32:registers|Registers[4][7]~30759                                                                  ; |Mips_Top|Registers32:registers|Registers[4][7]~30759                                                            ; combout          ;
; |Mips_Top|Registers32:registers|Registers[2][8]~30782                                                                  ; |Mips_Top|Registers32:registers|Registers[2][8]~30782                                                            ; combout          ;
; |Mips_Top|Registers32:registers|Registers[30][9]~30789                                                                 ; |Mips_Top|Registers32:registers|Registers[30][9]~30789                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Registers[0][12]~30790                                                                 ; |Mips_Top|Registers32:registers|Registers[0][12]~30790                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Registers[4][15]~30794                                                                 ; |Mips_Top|Registers32:registers|Registers[4][15]~30794                                                           ; combout          ;
; |Mips_Top|clock_gen:clocks|state~99                                                                                    ; |Mips_Top|clock_gen:clocks|state~99                                                                              ; combout          ;
; |Mips_Top|clock_gen:clocks|state~100                                                                                   ; |Mips_Top|clock_gen:clocks|state~100                                                                             ; combout          ;
; |Mips_Top|clock_gen:clocks|state~101                                                                                   ; |Mips_Top|clock_gen:clocks|state~101                                                                             ; combout          ;
; |Mips_Top|Ifetch32:ifetch|pc_inc[2]                                                                                    ; |Mips_Top|Ifetch32:ifetch|pc_inc[2]                                                                              ; regout           ;
; |Mips_Top|Controler:controler|rd[1]                                                                                    ; |Mips_Top|Controler:controler|rd[1]                                                                              ; regout           ;
; |Mips_Top|Registers32:registers|WriteAddr~386                                                                          ; |Mips_Top|Registers32:registers|WriteAddr~386                                                                    ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr~387                                                                          ; |Mips_Top|Registers32:registers|WriteAddr~387                                                                    ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr~388                                                                          ; |Mips_Top|Registers32:registers|WriteAddr~388                                                                    ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr~389                                                                          ; |Mips_Top|Registers32:registers|WriteAddr~389                                                                    ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr~390                                                                          ; |Mips_Top|Registers32:registers|WriteAddr~390                                                                    ; combout          ;
; |Mips_Top|Controler:controler|rw~728                                                                                   ; |Mips_Top|Controler:controler|rw~728                                                                             ; combout          ;
; |Mips_Top|Registers32:registers|Registers[30][0]                                                                       ; |Mips_Top|Registers32:registers|Registers[30][0]                                                                 ; regout           ;
; |Mips_Top|Registers32:registers|Mux63~611                                                                              ; |Mips_Top|Registers32:registers|Mux63~611                                                                        ; combout          ;
; |Mips_Top|Registers32:registers|Mux63~614                                                                              ; |Mips_Top|Registers32:registers|Mux63~614                                                                        ; combout          ;
; |Mips_Top|Registers32:registers|Mux63~615                                                                              ; |Mips_Top|Registers32:registers|Mux63~615                                                                        ; combout          ;
; |Mips_Top|Registers32:registers|Mux31~610                                                                              ; |Mips_Top|Registers32:registers|Mux31~610                                                                        ; combout          ;
; |Mips_Top|Registers32:registers|Mux31~613                                                                              ; |Mips_Top|Registers32:registers|Mux31~613                                                                        ; combout          ;
; |Mips_Top|Registers32:registers|Mux31~614                                                                              ; |Mips_Top|Registers32:registers|Mux31~614                                                                        ; combout          ;
; |Mips_Top|Controler:controler|aluop~176                                                                                ; |Mips_Top|Controler:controler|aluop~176                                                                          ; combout          ;
; |Mips_Top|clock_gen:clocks|Selector3~29                                                                                ; |Mips_Top|clock_gen:clocks|Selector3~29                                                                          ; combout          ;
; |Mips_Top|Ifetch32:ifetch|pc_inc[3]                                                                                    ; |Mips_Top|Ifetch32:ifetch|pc_inc[3]                                                                              ; regout           ;
; |Mips_Top|Ifetch32:ifetch|pc_inc[4]                                                                                    ; |Mips_Top|Ifetch32:ifetch|pc_inc[4]                                                                              ; regout           ;
; |Mips_Top|Controler:controler|rw~729                                                                                   ; |Mips_Top|Controler:controler|rw~729                                                                             ; combout          ;
; |Mips_Top|Controler:controler|rd~546                                                                                   ; |Mips_Top|Controler:controler|rd~546                                                                             ; combout          ;
; |Mips_Top|Registers32:registers|Registers~30800                                                                        ; |Mips_Top|Registers32:registers|Registers~30800                                                                  ; combout          ;
; |Mips_Top|Registers32:registers|Registers~30801                                                                        ; |Mips_Top|Registers32:registers|Registers~30801                                                                  ; combout          ;
; |Mips_Top|Registers32:registers|Registers[2][23]~30819                                                                 ; |Mips_Top|Registers32:registers|Registers[2][23]~30819                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Registers[30][17]~30826                                                                ; |Mips_Top|Registers32:registers|Registers[30][17]~30826                                                          ; combout          ;
; |Mips_Top|Registers32:registers|Registers[0][23]~30827                                                                 ; |Mips_Top|Registers32:registers|Registers[0][23]~30827                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Registers[4][26]~30831                                                                 ; |Mips_Top|Registers32:registers|Registers[4][26]~30831                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Registers[28][29]~30834                                                                ; |Mips_Top|Registers32:registers|Registers[28][29]~30834                                                          ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~1051                                                                  ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~1051                                                            ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14154                                                                 ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14154                                                           ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14162                                                                 ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14162                                                           ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~930                                                                   ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~930                                                             ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14179                                                                 ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14179                                                           ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14182                                                                 ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14182                                                           ; combout          ;
; |Mips_Top|Registers32:registers|datasrc~39                                                                             ; |Mips_Top|Registers32:registers|datasrc~39                                                                       ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~1050                                                                  ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~1050                                                            ; combout          ;
; |Mips_Top|clock_gen:clocks|Selector6~29                                                                                ; |Mips_Top|clock_gen:clocks|Selector6~29                                                                          ; combout          ;
; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14356                                                                 ; |Mips_Top|ALU32:alu|shifter32_var:myshift|outreg~14356                                                           ; combout          ;
; |Mips_Top|Controler:controler|aluop~177                                                                                ; |Mips_Top|Controler:controler|aluop~177                                                                          ; combout          ;
; |Mips_Top|Controler:controler|ib~45                                                                                    ; |Mips_Top|Controler:controler|ib~45                                                                              ; combout          ;
; |Mips_Top|Controler:controler|jr~60                                                                                    ; |Mips_Top|Controler:controler|jr~60                                                                              ; combout          ;
; |Mips_Top|Controler:controler|rd~547                                                                                   ; |Mips_Top|Controler:controler|rd~547                                                                             ; combout          ;
; |Mips_Top|Controler:controler|rd~548                                                                                   ; |Mips_Top|Controler:controler|rd~548                                                                             ; combout          ;
; |Mips_Top|Controler:controler|alusrc~67                                                                                ; |Mips_Top|Controler:controler|alusrc~67                                                                          ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~614                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~614                                                                      ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~615                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~615                                                                      ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~616                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~616                                                                      ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~617                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~617                                                                      ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl~618                                                                            ; |Mips_Top|ALUDecoder:aludecoder|aluctrl~618                                                                      ; combout          ;
; |Mips_Top|ALU32:alu|add32:myadd|P0[10]~13                                                                              ; |Mips_Top|ALU32:alu|add32:myadd|P0[10]~13                                                                        ; combout          ;
; |Mips_Top|ALU32:alu|add32:myadd|P0[15]~18                                                                              ; |Mips_Top|ALU32:alu|add32:myadd|P0[15]~18                                                                        ; combout          ;
; |Mips_Top|ALU32:alu|add32:myadd|P0[14]~19                                                                              ; |Mips_Top|ALU32:alu|add32:myadd|P0[14]~19                                                                        ; combout          ;
; |Mips_Top|ALU32:al