mips_top.sim.rpt

是verilog做的简化mips32指令系统。 有些小问题

; |Mips_Top|ALU32:alu|Add0~639                                                                                           ; |Mips_Top|ALU32:alu|Add0~639                                                                                     ; sumout           ;
; |Mips_Top|clock_gen:clocks|aludecoderclk                                                                               ; |Mips_Top|clock_gen:clocks|aludecoderclk                                                                         ; regout           ;
; |Mips_Top|Registers32:registers|write_data[0]                                                                          ; |Mips_Top|Registers32:registers|write_data[0]                                                                    ; regout           ;
; |Mips_Top|clock_gen:clocks|dmemoryclk                                                                                  ; |Mips_Top|clock_gen:clocks|dmemoryclk                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~507                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~507                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~507                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~508                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~511                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~511                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~511                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~512                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~515                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~515                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~515                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~516                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~519                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~519                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~519                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~520                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~523                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~523                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~523                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~524                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~527                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~527                                                                               ; sumout           ;
; |Mips_Top|Ifetch32:ifetch|Add1~527                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~528                                                                               ; cout             ;
; |Mips_Top|Ifetch32:ifetch|Add1~531                                                                                     ; |Mips_Top|Ifetch32:ifetch|Add1~531                                                                               ; sumout           ;
; |Mips_Top|ALU32:alu|Mux33~48                                                                                           ; |Mips_Top|ALU32:alu|Mux33~48                                                                                     ; combout          ;
; |Mips_Top|clock_gen:clocks|state.S7                                                                                    ; |Mips_Top|clock_gen:clocks|state.S7                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|Selector0~29                                                                                ; |Mips_Top|clock_gen:clocks|Selector0~29                                                                          ; combout          ;
; |Mips_Top|clock_gen:clocks|state.S6                                                                                    ; |Mips_Top|clock_gen:clocks|state.S6                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|state~96                                                                                    ; |Mips_Top|clock_gen:clocks|state~96                                                                              ; combout          ;
; |Mips_Top|clock_gen:clocks|state~0                                                                                     ; |Mips_Top|clock_gen:clocks|state~0                                                                               ; combout          ;
; |Mips_Top|SignExt32:signext|offset[2]                                                                                  ; |Mips_Top|SignExt32:signext|offset[2]                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|next_pc~1540                                                                                 ; |Mips_Top|Ifetch32:ifetch|next_pc~1540                                                                           ; combout          ;
; |Mips_Top|SignExt32:signext|offset[3]                                                                                  ; |Mips_Top|SignExt32:signext|offset[3]                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|next_pc~1541                                                                                 ; |Mips_Top|Ifetch32:ifetch|next_pc~1541                                                                           ; combout          ;
; |Mips_Top|SignExt32:signext|offset[4]                                                                                  ; |Mips_Top|SignExt32:signext|offset[4]                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|next_pc~1542                                                                                 ; |Mips_Top|Ifetch32:ifetch|next_pc~1542                                                                           ; combout          ;
; |Mips_Top|SignExt32:signext|offset[5]                                                                                  ; |Mips_Top|SignExt32:signext|offset[5]                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|next_pc~1543                                                                                 ; |Mips_Top|Ifetch32:ifetch|next_pc~1543                                                                           ; combout          ;
; |Mips_Top|SignExt32:signext|offset[6]                                                                                  ; |Mips_Top|SignExt32:signext|offset[6]                                                                            ; regout           ;
; |Mips_Top|Ifetch32:ifetch|next_pc~1544                                                                                 ; |Mips_Top|Ifetch32:ifetch|next_pc~1544                                                                           ; combout          ;
; |Mips_Top|SignExt32:signext|offset[7]                                                                                  ; |Mips_Top|SignExt32:signext|offset[7]                                                                            ; regout           ;
; |Mips_Top|SignExt32:signext|offset[8]                                                                                  ; |Mips_Top|SignExt32:signext|offset[8]                                                                            ; regout           ;
; |Mips_Top|SignExt32:signext|offset[9]                                                                                  ; |Mips_Top|SignExt32:signext|offset[9]                                                                            ; regout           ;
; |Mips_Top|SignExt32:signext|offset[10]                                                                                 ; |Mips_Top|SignExt32:signext|offset[10]                                                                           ; regout           ;
; |Mips_Top|SignExt32:signext|offset[11]                                                                                 ; |Mips_Top|SignExt32:signext|offset[11]                                                                           ; regout           ;
; |Mips_Top|clock_gen:clocks|state.S5                                                                                    ; |Mips_Top|clock_gen:clocks|state.S5                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|state~97                                                                                    ; |Mips_Top|clock_gen:clocks|state~97                                                                              ; combout          ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl[1]                                                                             ; |Mips_Top|ALUDecoder:aludecoder|aluctrl[1]                                                                       ; regout           ;
; |Mips_Top|ALUDecoder:aludecoder|aluctrl[3]                                                                             ; |Mips_Top|ALUDecoder:aludecoder|aluctrl[3]                                                                       ; regout           ;
; |Mips_Top|clock_gen:clocks|state.S4                                                                                    ; |Mips_Top|clock_gen:clocks|state.S4                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|state~98                                                                                    ; |Mips_Top|clock_gen:clocks|state~98                                                                              ; combout          ;
; |Mips_Top|clock_gen:clocks|state.S2                                                                                    ; |Mips_Top|clock_gen:clocks|state.S2                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|state.S3                                                                                    ; |Mips_Top|clock_gen:clocks|state.S3                                                                              ; regout           ;
; |Mips_Top|clock_gen:clocks|Selector2~29                                                                                ; |Mips_Top|clock_gen:clocks|Selector2~29                                                                          ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr[2]                                                                           ; |Mips_Top|Registers32:registers|WriteAddr[2]                                                                     ; regout           ;
; |Mips_Top|Registers32:registers|WriteAddr[1]                                                                           ; |Mips_Top|Registers32:registers|WriteAddr[1]                                                                     ; regout           ;
; |Mips_Top|Registers32:registers|Decoder0~850                                                                           ; |Mips_Top|Registers32:registers|Decoder0~850                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|WriteAddr[4]                                                                           ; |Mips_Top|Registers32:registers|WriteAddr[4]                                                                     ; regout           ;
; |Mips_Top|Registers32:registers|WriteAddr[3]                                                                           ; |Mips_Top|Registers32:registers|WriteAddr[3]                                                                     ; regout           ;
; |Mips_Top|Registers32:registers|Decoder0~851                                                                           ; |Mips_Top|Registers32:registers|Decoder0~851                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Decoder0~852                                                                           ; |Mips_Top|Registers32:registers|Decoder0~852                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Decoder0~858                                                                           ; |Mips_Top|Registers32:registers|Decoder0~858                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Decoder0~859                                                                           ; |Mips_Top|Registers32:registers|Decoder0~859                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Registers[2][7]~30742                                                                  ; |Mips_Top|Registers32:registers|Registers[2][7]~30742                                                            ; combout          ;
; |Mips_Top|Registers32:registers|Decoder0~860                                                                           ; |Mips_Top|Registers32:registers|Decoder0~860                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Registers[6][1]~30746                                                                  ; |Mips_Top|Registers32:registers|Registers[6][1]~30746                                                            ; combout          ;
; |Mips_Top|Registers32:registers|Registers[30][4]~30749                                                                 ; |Mips_Top|Registers32:registers|Registers[30][4]~30749                                                           ; combout          ;
; |Mips_Top|Registers32:registers|Decoder0~861                                                                           ; |Mips_Top|Registers32:registers|Decoder0~861                                                                     ; combout          ;
; |Mips_Top|Registers32:registers|Registers[0][5]~30750                                                                  ; |Mips_Top|Registers32:registers|Registers[0][5]~30750                                                            ; combout          ;
; |Mips_Top|clock_gen:clocks|Selector4~29                                                                                ; |Mips_Top|clock_gen:clocks|Selector4~29                                                                          ; combout          ;
; |Mips_Top|Controler:controler|alusrc                                                                                   ; |Mips_Top|Controler:controler|alusrc                                                                             ; regout           ;
; |Mips_Top|ALU32:alu|Mux1~42                                                                                            ; |Mips_Top|ALU32:alu|Mux1~42                                                                                      ; combout          ;
; |Mips_Top|ALU32:alu|Mux1~44                                                                                            ; |Mips_Top|ALU32:alu|Mux1~44                                                                                      ; combout          ;
; |Mips_Top|ALU32:alu|WideOr2                                                                                            ; |Mips_Top|ALU32:alu|WideOr2                                                                                      ; combout          ;
; |Mips_Top|SignExt32:signext|offset[17]                                                                                 ; |Mips_Top|SignExt32:signext|offset[17]                                                                           ; regout           ;
; |Mips_Top|SignExt32:signext|offset[16]                                                                                 ; |Mips_Top|SignExt32:signext|offset[16]                                                                           ; regout           ;