mips_top.sim.rpt

是verilog做的简化mips32指令系统。 有些小问题

; Display complete 1/0 value coverage report                                                 ; On           ; On            ;
; Display missing 1-value coverage report                                                    ; On           ; On            ;
; Display missing 0-value coverage report                                                    ; On           ; On            ;
; Detect setup and hold time violations                                                      ; On           ; Off           ;
; Detect glitches                                                                            ; Off          ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off          ; Off           ;
; Generate Signal Activity File                                                              ; Off          ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off          ; Off           ;
; Group bus channels in simulation results                                                   ; Off          ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On           ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE   ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off          ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off          ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto         ; Auto          ;
+--------------------------------------------------------------------------------------------+--------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------------------------------+
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;       8.78 % ;
; Total nodes checked                                 ; 4158         ;
; Total output ports checked                          ; 4271         ;
; Total output ports with complete 1/0-value coverage ; 375          ;
; Total output ports with no 1/0-value coverage       ; 1985         ;
; Total output ports with no 1-value coverage         ; 3524         ;
; Total output ports with no 0-value coverage         ; 2357         ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                  ;
+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                              ; Output Port Name                                                                                                 ; Output Port Type ;
+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+------------------+
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a0  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[0]  ; portadataout0    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a0  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[1]  ; portadataout1    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a0  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[2]  ; portadataout2    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a0  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[3]  ; portadataout3    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a4  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[4]  ; portadataout0    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a4  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[5]  ; portadataout1    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a4  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[6]  ; portadataout2    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a4  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[7]  ; portadataout3    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a8  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[8]  ; portadataout0    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a8  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[9]  ; portadataout1    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a8  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[10] ; portadataout2    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a8  ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[11] ; portadataout3    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a12 ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[12] ; portadataout0    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a12 ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[13] ; portadataout1    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a12 ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[14] ; portadataout2    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a12 ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[15] ; portadataout3    ;
; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|ram_block1a16 ; |Mips_Top|Ifetch32:ifetch|lpm_rom:prgrom|altrom:srom|altsyncram:rom_block|altsyncram_7201:auto_generated|q_a[16] ; portadataout0    ;