mips_top.v

是verilog做的简化mips32指令系统。 有些小问题

`timescale 10ns/1ns
module Mips_Top(reset,clock,instruction);
	input reset;
	input clock;
	output [31:0] instruction;
	wire [31:0] instruction,
				memdata,
				regdata1,
				regdata2,
				pc_inc,
				next_pc,
				aluimmediate,
				aluresult;
	wire aluzero,j,jr,ib,b,alusrc,rdws,rw,mr,mw,mtr,alucout,alucin;
	wire [1:0] aluop;
	wire [1:0] rwdw;
	wire [1:0] mwdw;
	wire [1:0] rd;
	wire [3:0] aluctrl;
	wire registersclk,controlerclk,dmemoryclk,ifetchclk,aludecoderclk,aluclk,sigextclk; 
	clock_gen clocks(.clock(clock),
					 .reset(reset),
					 .registersclk(registersclk),
					 .controlerclk(controlerclk),
					 .dmemoryclk(dmemoryclk),
					 .ifetchclk(ifetchclk),
					 .aludecoderclk(aludecoderclk),
					 .aluclk(aluclk),
					 .sigextclk(sigextclk)); 

	Ifetch32 ifetch(.AluZero(aluzero),
					.j(j),
					.jr(jr),
					.ib(ib),
					.b(b),
					.clk(ifetchclk),
					.reset(reset),
					.ReadData1(regdata1),
					.offset(aluimmediate),
					.instruction(instruction),
					.pc_inc(pc_inc),
					/*.next_pc()*/);
					
	Registers32 registers(  .instruction(instruction),
							.reset(reset),
							.pc_inc(pc_inc),//pc+4 
							.memdata(memdata),
							.aluresult(aluresult),
							.rd(rd),
							.rw(rw),
							.rwdw(rwdw),
							.mtr(mtr),
							.rwds(rwds),
							.clk(registersclk),
							.Read1(regdata1),
							.Read2(regdata2));
							
	Controler controler(.opcode(instruction[31:26]),
						.clk(controlerclk),
						.rd(rd),
						.j(j),
						.jr(jr),
						.ib(ib),
						.b(b),
						.aluop(aluop),
						.alusrc(alusrc),
						.rwds(rwds),
						.rw(rw),
						.rwdw(rwdw),
						.mwdw(mwdw),
						.mr(mr),
						.mw(mw),
						.mtr(mtr));
						
	ALUDecoder aludecoder(  .funct(instruction[5:0]),
							.aluop(aluop),
							.clk(aludecoderclk),
							.aluctrl(aluctrl)); 
							
	SignExt32 signext(  .immediate(instruction[15:0]),
						.clk(sigextclk),
						.Extend(aluimmediate),
						/*.offset(offset)*/);
						
	ALU32 alu(  .r1(regdata1),
				.r2(regdata2),
				.im(aluimmediate),
				.cin(alucin),
				.aluctrl(aluctrl),
				.ALUSrc(alusrc),
				.clk(aluclk),
				.zero(aluzero),
				.result(aluresult),
				.cout(alucout)); 
				
	Dmemory32 dmemory(  .address(aluresult),
						.write_data(regdata2),
						.mr(mr),
						.mw(mw),
						.mwdw(mwdw),
						.clk(dmemoryclk),
						.read_data(memdata));	
endmodule