📄 counter.rpt
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_EQ040 = !data3 & !_LC6_D11 & _LC8_D14
# data3 & !_LC6_D11 & !_LC8_D14
# !data3 & !_LC3_D9 & _LC8_D14
# data3 & !_LC3_D9 & !_LC8_D14
# data3 & _LC3_D9 & _LC6_D11 & _LC8_D14
# !data3 & _LC3_D9 & _LC6_D11 & !_LC8_D14;
-- Node name is ':202'
-- Equation name is '_LC6_D9', type is buried
_LC6_D9 = LCELL( _EQ041);
_EQ041 = _LC6_D7 & !_LC6_D11
# _LC6_D7 & _LC6_D8
# !_LC6_D7 & !_LC6_D8 & _LC6_D11;
-- Node name is ':220'
-- Equation name is '_LC4_D1', type is buried
!_LC4_D1 = _LC4_D1~NOT;
_LC4_D1~NOT = LCELL( _EQ042);
_EQ042 = !_LC5_D11 & !_LC6_D14;
-- Node name is ':348'
-- Equation name is '_LC8_D3', type is buried
_LC8_D3 = LCELL( _EQ043);
_EQ043 = _LC1_D7 & _LC8_D8
# _LC1_D7 & _LC3_D7;
-- Node name is '~371~1'
-- Equation name is '~371~1', location is LC8_D5, type is buried.
-- synthesized logic cell
_LC8_D5 = LCELL(!_LC5_D7);
-- Node name is '~371~2'
-- Equation name is '~371~2', location is LC7_D3, type is buried.
-- synthesized logic cell
_LC7_D3 = LCELL( _EQ044);
_EQ044 = _LC8_D5
# !change5 & !_LC5_D7;
-- Node name is ':371'
-- Equation name is '_LC4_D3', type is buried
_LC4_D3 = LCELL( _EQ045);
_EQ045 = _LC7_D3
# change4 & _LC4_D7
# !change4 & !_LC4_D7
# _LC8_D3;
-- Node name is ':390'
-- Equation name is '_LC2_D5', type is buried
!_LC2_D5 = _LC2_D5~NOT;
_LC2_D5~NOT = LCELL( _EQ046);
_EQ046 = _LC1_D5 & _LC5_D5
# _LC5_D5 & !_LC6_D5
# !_LC1_D5 & _LC4_D3 & !_LC5_D5 & _LC6_D5
# !_LC4_D3 & _LC5_D5;
-- Node name is ':396'
-- Equation name is '_LC3_D5', type is buried
!_LC3_D5 = _LC3_D5~NOT;
_LC3_D5~NOT = LCELL( _EQ047);
_EQ047 = _LC1_D5 & _LC6_D5
# !_LC1_D5 & _LC4_D3 & !_LC6_D5
# !_LC4_D3 & _LC6_D5;
-- Node name is ':402'
-- Equation name is '_LC3_D3', type is buried
!_LC3_D3 = _LC3_D3~NOT;
_LC3_D3~NOT = LCELL( _EQ048);
_EQ048 = change5 & _LC5_D3 & !_LC5_D7
# !change5 & _LC5_D3 & _LC5_D7
# change5 & !_LC4_D3 & !_LC5_D7
# !change5 & !_LC4_D3 & _LC5_D7
# change5 & _LC4_D3 & !_LC5_D3 & _LC5_D7
# !change5 & _LC4_D3 & !_LC5_D3 & !_LC5_D7;
-- Node name is ':408'
-- Equation name is '_LC1_D3', type is buried
_LC1_D3 = LCELL( _EQ049);
_EQ049 = !_LC4_D3 & !_LC4_D7
# !_LC4_D7 & _LC6_D3
# _LC1_D7 & !_LC4_D7
# !_LC1_D7 & _LC4_D3 & _LC4_D7 & !_LC6_D3;
-- Node name is ':414'
-- Equation name is '_LC2_D3', type is buried
_LC2_D3 = LCELL( _EQ050);
_EQ050 = _LC1_D7 & !_LC4_D3
# _LC1_D7 & _LC6_D3
# !_LC1_D7 & _LC4_D3 & !_LC6_D3;
-- Node name is ':420'
-- Equation name is '_LC1_D8', type is buried
_LC1_D8 = LCELL( _EQ051);
_EQ051 = _LC3_D7 & !_LC4_D3
# !_LC3_D7 & _LC4_D3 & _LC8_D8
# _LC3_D7 & !_LC8_D8;
-- Node name is ':503'
-- Equation name is '_LC6_D6', type is buried
_LC6_D6 = LCELL( _EQ052);
_EQ052 = _LC3_D6
# add & !_LC4_D1 & _LC4_D5;
-- Node name is ':505'
-- Equation name is '_LC3_D6', type is buried
_LC3_D6 = LCELL( _EQ053);
_EQ053 = !add & _LC2_D5 & !_LC3_D3 & !_LC3_D5;
-- Node name is ':509'
-- Equation name is '_LC4_D6', type is buried
_LC4_D6 = LCELL( _EQ054);
_EQ054 = _LC1_D6 & _LC3_D5
# _LC2_D6 & _LC6_D14;
-- Node name is ':515'
-- Equation name is '_LC7_D6', type is buried
_LC7_D6 = LCELL( _EQ055);
_EQ055 = _LC1_D6 & _LC3_D3
# _LC2_D6 & _LC5_D11;
-- Node name is '~516~1'
-- Equation name is '~516~1', location is LC2_D6, type is buried.
-- synthesized logic cell
_LC2_D6 = LCELL( _EQ056);
_EQ056 = add & !_LC4_D5;
-- Node name is '~517~1'
-- Equation name is '~517~1', location is LC1_D6, type is buried.
-- synthesized logic cell
_LC1_D6 = LCELL( _EQ057);
_EQ057 = !add & !_LC2_D5;
-- Node name is ':521'
-- Equation name is '_LC1_D13', type is buried
_LC1_D13 = LCELL( _EQ058);
_EQ058 = _LC1_D3 & _LC5_D6
# _LC8_D6 & _LC8_D11;
-- Node name is ':527'
-- Equation name is '_LC5_D9', type is buried
_LC5_D9 = LCELL( _EQ059);
_EQ059 = _LC2_D3 & _LC5_D6
# _LC8_D6 & _LC8_D9;
-- Node name is ':533'
-- Equation name is '_LC7_D9', type is buried
_LC7_D9 = LCELL( _EQ060);
_EQ060 = _LC1_D8 & _LC5_D6
# _LC6_D9 & _LC8_D6;
-- Node name is ':539'
-- Equation name is '_LC5_D8', type is buried
_LC5_D8 = LCELL( _EQ061);
_EQ061 = _LC3_D8
# _LC6_D8 & !_LC6_D11 & _LC8_D6
# !_LC6_D8 & _LC6_D11 & _LC8_D6;
-- Node name is ':541'
-- Equation name is '_LC3_D8', type is buried
_LC3_D8 = LCELL( _EQ062);
_EQ062 = !_LC4_D3 & _LC5_D6 & _LC8_D8
# _LC4_D3 & _LC5_D6 & !_LC8_D8;
-- Node name is ':545'
-- Equation name is '_LC4_D9', type is buried
_LC4_D9 = LCELL( _EQ063);
_EQ063 = change0 & !data0 & _LC5_D6
# change0 & !data0 & _LC8_D6
# !change0 & data0 & _LC5_D6
# !change0 & data0 & _LC8_D6;
-- Node name is '~546~1'
-- Equation name is '~546~1', location is LC8_D6, type is buried.
-- synthesized logic cell
_LC8_D6 = LCELL( _EQ064);
_EQ064 = add & !_LC4_D5
# add & !_LC4_D1;
-- Node name is '~547~1'
-- Equation name is '~547~1', location is LC5_D6, type is buried.
-- synthesized logic cell
_LC5_D6 = LCELL( _EQ065);
_EQ065 = !add & !_LC2_D5
# !add & !_LC3_D3 & !_LC3_D5;
Project Information g:\pldshiyan\counter\counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:10
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,374K
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