📄 counter.rpt
字号:
49 - - - 21 INPUT ^ 0 0 0 8 clr
43 - - - 30 INPUT ^ 0 0 0 5 data0
41 - - - 31 INPUT ^ 0 0 0 4 data1
39 - - - 33 INPUT ^ 0 0 0 4 data2
38 - - - 34 INPUT ^ 0 0 0 7 data3
51 - - - 20 INPUT ^ 0 0 0 8 en
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\pldshiyan\counter\counter.rpt
counter
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
102 - - A -- OUTPUT 0 1 0 0 mm0
117 - - - 08 OUTPUT 0 1 0 0 mm1
118 - - - 09 OUTPUT 0 1 0 0 mm2
119 - - - 13 OUTPUT 0 1 0 0 mm3
120 - - - 14 OUTPUT 0 1 0 0 mm4
18 - - C -- OUTPUT 0 1 0 0 mm5
19 - - D -- OUTPUT 0 1 0 0 mm6
20 - - D -- OUTPUT 0 1 0 0 mm7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\pldshiyan\counter\counter.rpt
counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 08 OR2 2 2 0 2 |LPM_ADD_SUB:125|addcore:adder|pcarry1
- 2 - D 07 OR2 1 2 0 4 |LPM_ADD_SUB:125|addcore:adder|pcarry2
- 3 - D 14 OR2 1 3 0 6 |LPM_ADD_SUB:125|addcore:adder|:133
- 8 - D 07 OR2 1 3 0 4 |LPM_ADD_SUB:125|addcore:adder|:152
- 3 - D 11 OR2 0 2 0 1 |LPM_ADD_SUB:125|addcore:adder|:153
- 2 - D 14 OR2 0 3 0 2 |LPM_ADD_SUB:125|addcore:adder|:154
- 7 - D 05 OR2 0 4 0 1 |LPM_ADD_SUB:125|addcore:adder|:155
- 6 - D 08 OR2 2 2 0 3 |LPM_ADD_SUB:125|addcore:adder|:156
- 6 - D 07 OR2 1 2 0 2 |LPM_ADD_SUB:125|addcore:adder|:157
- 8 - D 14 OR2 s 0 2 0 1 |LPM_ADD_SUB:125|addcore:adder|~158~1
- 3 - D 09 OR2 0 2 0 2 |LPM_ADD_SUB:162|addcore:adder|pcarry2
- 4 - D 14 OR2 1 3 0 4 |LPM_ADD_SUB:162|addcore:adder|:129
- 4 - D 11 OR2 0 4 0 2 |LPM_ADD_SUB:162|addcore:adder|:137
- 4 - D 08 OR2 2 2 0 2 |LPM_ADD_SUB:343|addcore:adder|pcarry1
- 7 - D 07 OR2 1 2 0 3 |LPM_ADD_SUB:343|addcore:adder|pcarry2
- 5 - D 07 OR2 1 3 0 6 |LPM_ADD_SUB:343|addcore:adder|pcarry4
- 4 - D 07 OR2 1 3 0 3 |LPM_ADD_SUB:343|addcore:adder|:152
- 6 - D 05 OR2 0 3 0 2 |LPM_ADD_SUB:343|addcore:adder|:154
- 5 - D 05 OR2 0 4 0 1 |LPM_ADD_SUB:343|addcore:adder|:155
- 8 - D 08 OR2 2 2 0 4 |LPM_ADD_SUB:343|addcore:adder|:156
- 3 - D 07 OR2 1 2 0 3 |LPM_ADD_SUB:343|addcore:adder|:157
- 1 - D 07 OR2 1 2 0 4 |LPM_ADD_SUB:343|addcore:adder|:158
- 5 - D 03 OR2 0 3 0 2 |LPM_ADD_SUB:380|addcore:adder|pcarry4
- 1 - D 05 OR2 0 3 0 2 |LPM_ADD_SUB:380|addcore:adder|pcarry5
- 6 - D 03 AND2 0 2 0 3 |LPM_ADD_SUB:380|addcore:adder|:125
- 2 - D 02 DFFE + 2 1 1 2 change7 (:25)
- 1 - D 14 DFFE + 2 1 1 4 change6 (:26)
- 7 - D 14 DFFE + 2 1 1 10 change5 (:27)
- 8 - D 13 DFFE + 2 1 1 6 change4 (:28)
- 5 - D 14 DFFE + 2 1 1 7 change3 (:29)
- 2 - D 09 DFFE + 2 1 1 4 change2 (:30)
- 7 - D 08 DFFE + 2 1 1 4 change1 (:31)
- 1 - D 09 DFFE + 2 1 1 5 change0 (:32)
- 1 - D 11 AND2 s 0 1 0 1 ~153~1
- 2 - D 11 OR2 s 0 3 0 1 ~153~2
- 6 - D 11 OR2 0 4 0 6 :153
- 4 - D 05 OR2 ! 0 4 0 3 :172
- 6 - D 14 OR2 ! 0 3 0 2 :178
- 5 - D 11 OR2 ! 0 4 0 2 :184
- 8 - D 11 OR2 0 2 0 1 :190
- 8 - D 09 OR2 1 3 0 1 :196
- 6 - D 09 OR2 0 3 0 1 :202
- 4 - D 01 AND2 ! 0 2 0 2 :220
- 8 - D 03 OR2 0 3 0 1 :348
- 8 - D 05 AND2 s 0 1 0 1 ~371~1
- 7 - D 03 OR2 s 0 3 0 1 ~371~2
- 4 - D 03 OR2 0 4 0 7 :371
- 2 - D 05 OR2 ! 0 4 0 3 :390
- 3 - D 05 OR2 ! 0 3 0 3 :396
- 3 - D 03 OR2 ! 0 4 0 3 :402
- 1 - D 03 OR2 0 4 0 1 :408
- 2 - D 03 OR2 0 3 0 1 :414
- 1 - D 08 OR2 0 3 0 1 :420
- 6 - D 06 OR2 1 3 0 1 :503
- 3 - D 06 AND2 1 3 0 1 :505
- 4 - D 06 OR2 0 4 0 1 :509
- 7 - D 06 OR2 0 4 0 1 :515
- 2 - D 06 AND2 s 1 1 0 2 ~516~1
- 1 - D 06 AND2 s 1 1 0 2 ~517~1
- 1 - D 13 OR2 0 4 0 1 :521
- 5 - D 09 OR2 0 4 0 1 :527
- 7 - D 09 OR2 0 4 0 1 :533
- 5 - D 08 OR2 0 4 0 1 :539
- 3 - D 08 OR2 0 3 0 1 :541
- 4 - D 09 OR2 1 3 0 1 :545
- 8 - D 06 OR2 s 1 2 0 5 ~546~1
- 5 - D 06 OR2 s 1 3 0 5 ~547~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\pldshiyan\counter\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 53/144( 36%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pldshiyan\counter\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: g:\pldshiyan\counter\counter.rpt
counter
** EQUATIONS **
add : INPUT;
clk : INPUT;
clr : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
en : INPUT;
-- Node name is ':32' = 'change0'
-- Equation name is 'change0', location is LC1_D9, type is buried.
change0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !clr & en & _LC4_D9
# change0 & !clr & !en;
-- Node name is ':31' = 'change1'
-- Equation name is 'change1', location is LC7_D8, type is buried.
change1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !clr & en & _LC5_D8
# change1 & !clr & !en;
-- Node name is ':30' = 'change2'
-- Equation name is 'change2', location is LC2_D9, type is buried.
change2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !clr & en & _LC7_D9
# change2 & !clr & !en;
-- Node name is ':29' = 'change3'
-- Equation name is 'change3', location is LC5_D14, type is buried.
change3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !clr & en & _LC5_D9
# change3 & !clr & !en;
-- Node name is ':28' = 'change4'
-- Equation name is 'change4', location is LC8_D13, type is buried.
change4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !clr & en & _LC1_D13
# change4 & !clr & !en;
-- Node name is ':27' = 'change5'
-- Equation name is 'change5', location is LC7_D14, type is buried.
change5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !clr & en & _LC7_D6
# change5 & !clr & !en;
-- Node name is ':26' = 'change6'
-- Equation name is 'change6', location is LC1_D14, type is buried.
change6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !clr & en & _LC4_D6
# change6 & !clr & !en;
-- Node name is ':25' = 'change7'
-- Equation name is 'change7', location is LC2_D2, type is buried.
change7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !clr & en & _LC6_D6
# change7 & !clr & !en;
-- Node name is 'mm0'
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