📄 ls160.rpt
字号:
- 6 - C 13 OR2 1 3 0 1 :169
- 8 - C 22 OR2 2 2 0 1 :207
- 6 - C 22 OR2 1 2 0 1 :213
- 8 - C 13 OR2 1 2 0 1 :219
- 3 - C 13 OR2 2 1 0 1 :225
- 2 - C 13 AND2 s 2 1 0 1 ~379~1
- 5 - C 22 AND2 2 1 1 0 :379
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: h:\pldshiyan\ls160\ls160.rpt
ls160
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 12/144( 8%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\pldshiyan\ls160\ls160.rpt
ls160
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: h:\pldshiyan\ls160\ls160.rpt
ls160
** EQUATIONS **
clk : INPUT;
clr : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
ld : INPUT;
p : INPUT;
t : INPUT;
-- Node name is 'count0'
-- Equation name is 'count0', type is output
count0 = _LC1_C13;
-- Node name is 'count1'
-- Equation name is 'count1', type is output
count1 = _LC7_C13;
-- Node name is 'count2'
-- Equation name is 'count2', type is output
count2 = _LC4_C22;
-- Node name is 'count3'
-- Equation name is 'count3', type is output
count3 = _LC2_C22;
-- Node name is 'tc'
-- Equation name is 'tc', type is output
tc = _LC5_C22;
-- Node name is '|LPM_ADD_SUB:89|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ001);
_EQ001 = _LC1_C13 & _LC7_C13;
-- Node name is ':10'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clr & _LC8_C22 & ld
# clr & data3 & !ld;
-- Node name is ':12'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = clr & _LC6_C22 & ld
# clr & data2 & !ld;
-- Node name is ':14'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = clr & _LC8_C13 & ld
# clr & data1 & !ld;
-- Node name is ':16'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = clr & _LC3_C13 & ld
# clr & data0 & !ld;
-- Node name is ':64'
-- Equation name is '_LC5_C13', type is buried
!_LC5_C13 = _LC5_C13~NOT;
_LC5_C13~NOT = LCELL( _EQ006);
_EQ006 = !_LC2_C22
# _LC4_C22
# _LC7_C13
# !_LC1_C13;
-- Node name is '~158~1'
-- Equation name is '~158~1', location is LC4_C13, type is buried.
-- synthesized logic cell
_LC4_C13 = LCELL( _EQ007);
_EQ007 = !_LC5_C13 & t;
-- Node name is ':158'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ008);
_EQ008 = _LC2_C22 & _LC4_C13 & !_LC4_C22
# !_LC1_C22 & _LC2_C22 & _LC4_C13
# _LC1_C22 & !_LC2_C22 & _LC4_C13 & _LC4_C22;
-- Node name is ':163'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = LCELL( _EQ009);
_EQ009 = !_LC1_C22 & _LC4_C13 & _LC4_C22
# _LC1_C22 & _LC4_C13 & !_LC4_C22
# _LC4_C22 & !t;
-- Node name is ':169'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ010);
_EQ010 = !_LC1_C13 & _LC4_C13 & _LC7_C13
# _LC1_C13 & _LC4_C13 & !_LC7_C13
# _LC7_C13 & !t;
-- Node name is ':207'
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ011);
_EQ011 = _LC7_C22 & p
# _LC2_C22 & !t
# _LC2_C22 & !p;
-- Node name is ':213'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = LCELL( _EQ012);
_EQ012 = _LC3_C22 & p
# _LC4_C22 & !p;
-- Node name is ':219'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ013);
_EQ013 = _LC6_C13 & p
# _LC7_C13 & !p;
-- Node name is ':225'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ014);
_EQ014 = _LC1_C13 & !t
# !_LC1_C13 & p & t
# _LC1_C13 & !p;
-- Node name is '~379~1'
-- Equation name is '~379~1', location is LC2_C13, type is buried.
-- synthesized logic cell
_LC2_C13 = LCELL( _EQ015);
_EQ015 = _LC5_C13 & ld & p;
-- Node name is ':379'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ016);
_EQ016 = clr & _LC2_C13 & t;
Project Information h:\pldshiyan\ls160\ls160.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,305K
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