📄 vote7.rpt
字号:
41 - - - 31 INPUT ^ 0 0 0 2 men2
43 - - - 30 INPUT ^ 0 0 0 3 men3
44 - - - 29 INPUT ^ 0 0 0 3 men4
46 - - - 27 INPUT ^ 0 0 0 2 men5
47 - - - 25 INPUT ^ 0 0 0 1 men6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\pldshiyan\vote7\vote7.rpt
vote7
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
20 - - D -- OUTPUT 0 0 0 0 LedFail
22 - - D -- OUTPUT 0 1 0 0 LedPass
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\pldshiyan\vote7\vote7.rpt
vote7
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - D 25 OR2 1 3 0 1 |LPM_ADD_SUB:350|addcore:adder|:60
- 3 - D 25 OR2 3 0 0 2 :210
- 1 - D 25 OR2 3 0 0 3 :216
- 5 - D 25 OR2 2 2 0 2 :284
- 4 - D 25 OR2 2 2 0 2 :290
- 2 - D 25 OR2 2 1 0 2 :296
- 7 - D 25 OR2 1 3 0 1 :324
- 6 - D 25 OR2 1 2 1 0 :364
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\pldshiyan\vote7\vote7.rpt
vote7
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 8/ 72( 11%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pldshiyan\vote7\vote7.rpt
vote7
** EQUATIONS **
men0 : INPUT;
men1 : INPUT;
men2 : INPUT;
men3 : INPUT;
men4 : INPUT;
men5 : INPUT;
men6 : INPUT;
-- Node name is 'LedFail'
-- Equation name is 'LedFail', type is output
LedFail = GND;
-- Node name is 'LedPass'
-- Equation name is 'LedPass', type is output
LedPass = _LC6_D25;
-- Node name is '|LPM_ADD_SUB:350|addcore:adder|:60' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_D25', type is buried
_LC8_D25 = LCELL( _EQ001);
_EQ001 = !_LC2_D25 & _LC5_D25 & !men5
# !_LC4_D25 & _LC5_D25
# _LC4_D25 & !_LC5_D25 & men5
# _LC2_D25 & _LC4_D25 & !_LC5_D25;
-- Node name is ':210'
-- Equation name is '_LC3_D25', type is buried
_LC3_D25 = LCELL( _EQ002);
_EQ002 = men1 & men2
# men0 & men2
# men0 & men1;
-- Node name is ':216'
-- Equation name is '_LC1_D25', type is buried
_LC1_D25 = LCELL( _EQ003);
_EQ003 = !men0 & men1 & !men2
# men0 & !men1 & !men2
# !men0 & !men1 & men2
# men0 & men1 & men2;
-- Node name is ':284'
-- Equation name is '_LC5_D25', type is buried
_LC5_D25 = LCELL( _EQ004);
_EQ004 = _LC1_D25 & _LC3_D25 & men4
# _LC3_D25 & men3 & men4
# _LC1_D25 & _LC3_D25 & men3;
-- Node name is ':290'
-- Equation name is '_LC4_D25', type is buried
_LC4_D25 = LCELL( _EQ005);
_EQ005 = !_LC1_D25 & _LC3_D25 & !men3
# !_LC3_D25 & men3 & men4
# _LC1_D25 & !_LC3_D25 & men4
# !_LC1_D25 & _LC3_D25 & !men4
# _LC1_D25 & !_LC3_D25 & men3
# _LC3_D25 & !men3 & !men4;
-- Node name is ':296'
-- Equation name is '_LC2_D25', type is buried
_LC2_D25 = LCELL( _EQ006);
_EQ006 = !_LC1_D25 & men3 & !men4
# _LC1_D25 & !men3 & !men4
# !_LC1_D25 & !men3 & men4
# _LC1_D25 & men3 & men4;
-- Node name is ':324'
-- Equation name is '_LC7_D25', type is buried
_LC7_D25 = LCELL( _EQ007);
_EQ007 = _LC2_D25 & _LC4_D25 & !_LC5_D25 & men5
# !_LC4_D25 & _LC5_D25
# !_LC2_D25 & _LC5_D25
# _LC5_D25 & !men5;
-- Node name is ':364'
-- Equation name is '_LC6_D25', type is buried
_LC6_D25 = LCELL( _EQ008);
_EQ008 = _LC7_D25 & !men6
# _LC8_D25 & men6;
Project Information g:\pldshiyan\vote7\vote7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:59
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:42
Timing SNF Extractor 00:00:03
Assembler 00:00:33
-------------------------- --------
Total Time 00:02:18
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,546K
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