📄 adder14.rpt
字号:
- 3 - D 13 OR2 4 0 0 1 |LPM_ADD_SUB:21|addcore:adder|:79
- 2 - D 14 OR2 2 1 0 1 |LPM_ADD_SUB:21|addcore:adder|:80
- 4 - D 14 OR2 2 1 0 2 |LPM_ADD_SUB:21|addcore:adder|:81
- 2 - D 13 OR2 4 0 0 2 |LPM_ADD_SUB:29|addcore:adder|:63
- 6 - D 14 OR2 2 2 0 2 |LPM_ADD_SUB:29|addcore:adder|:67
- 1 - D 14 OR2 1 3 1 0 :39
- 7 - D 14 OR2 1 2 1 0 :45
- 5 - D 14 OR2 1 2 1 0 :51
- 8 - D 13 OR2 3 1 1 0 :57
- 2 - D 10 OR2 3 0 1 0 :63
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: h:\pldshiyan\adder14\adder14.rpt
adder14
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 10/144( 6%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\pldshiyan\adder14\adder14.rpt
adder14
** EQUATIONS **
ci : INPUT;
OP10 : INPUT;
OP11 : INPUT;
OP12 : INPUT;
OP13 : INPUT;
OP20 : INPUT;
OP21 : INPUT;
OP22 : INPUT;
OP23 : INPUT;
-- Node name is 'result0'
-- Equation name is 'result0', type is output
result0 = _LC2_D10;
-- Node name is 'result1'
-- Equation name is 'result1', type is output
result1 = _LC8_D13;
-- Node name is 'result2'
-- Equation name is 'result2', type is output
result2 = _LC5_D14;
-- Node name is 'result3'
-- Equation name is 'result3', type is output
result3 = _LC7_D14;
-- Node name is 'result4'
-- Equation name is 'result4', type is output
result4 = _LC1_D14;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_D13', type is buried
_LC1_D13 = LCELL( _EQ001);
_EQ001 = OP11 & OP21
# OP10 & OP11 & OP20
# OP10 & OP20 & OP21;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_D14', type is buried
_LC3_D14 = LCELL( _EQ002);
_EQ002 = _LC1_D13 & OP12
# _LC1_D13 & OP22
# OP12 & OP22;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_D14', type is buried
_LC8_D14 = LCELL( _EQ003);
_EQ003 = _LC3_D14 & OP13
# _LC3_D14 & OP23
# OP13 & OP23;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|:79' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_D13', type is buried
_LC3_D13 = LCELL( _EQ004);
_EQ004 = OP10 & OP11 & OP20 & OP21
# !OP10 & OP11 & !OP21
# OP11 & !OP20 & !OP21
# !OP10 & !OP11 & OP21
# !OP11 & !OP20 & OP21
# OP10 & !OP11 & OP20 & !OP21;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|:80' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_D14', type is buried
_LC2_D14 = LCELL( _EQ005);
_EQ005 = _LC1_D13 & OP12 & OP22
# !_LC1_D13 & OP12 & !OP22
# !_LC1_D13 & !OP12 & OP22
# _LC1_D13 & !OP12 & !OP22;
-- Node name is '|LPM_ADD_SUB:21|addcore:adder|:81' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_D14', type is buried
_LC4_D14 = LCELL( _EQ006);
_EQ006 = _LC3_D14 & OP13 & OP23
# !_LC3_D14 & OP13 & !OP23
# !_LC3_D14 & !OP13 & OP23
# _LC3_D14 & !OP13 & !OP23;
-- Node name is '|LPM_ADD_SUB:29|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D13', type is buried
_LC2_D13 = LCELL( _EQ007);
_EQ007 = OP10 & !OP11 & !OP20 & OP21
# OP10 & OP11 & !OP20 & !OP21
# !OP10 & !OP11 & OP20 & OP21
# !OP10 & OP11 & OP20 & !OP21;
-- Node name is '|LPM_ADD_SUB:29|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_D14', type is buried
_LC6_D14 = LCELL( _EQ008);
_EQ008 = !_LC1_D13 & _LC2_D13 & !OP12 & OP22
# _LC1_D13 & _LC2_D13 & !OP12 & !OP22
# _LC1_D13 & _LC2_D13 & OP12 & OP22
# !_LC1_D13 & _LC2_D13 & OP12 & !OP22;
-- Node name is ':39'
-- Equation name is '_LC1_D14', type is buried
_LC1_D14 = LCELL( _EQ009);
_EQ009 = ci & _LC4_D14 & _LC6_D14 & !_LC8_D14
# !_LC6_D14 & _LC8_D14
# !_LC4_D14 & _LC8_D14
# !ci & _LC8_D14;
-- Node name is ':45'
-- Equation name is '_LC7_D14', type is buried
_LC7_D14 = LCELL( _EQ010);
_EQ010 = !ci & _LC4_D14
# ci & !_LC4_D14 & _LC6_D14
# _LC4_D14 & !_LC6_D14;
-- Node name is ':51'
-- Equation name is '_LC5_D14', type is buried
_LC5_D14 = LCELL( _EQ011);
_EQ011 = !ci & _LC2_D14
# ci & _LC2_D13 & !_LC2_D14
# !_LC2_D13 & _LC2_D14;
-- Node name is ':57'
-- Equation name is '_LC8_D13', type is buried
_LC8_D13 = LCELL( _EQ012);
_EQ012 = !ci & _LC3_D13
# _LC3_D13 & OP10 & OP20
# _LC3_D13 & !OP10 & !OP20
# ci & !_LC3_D13 & OP10 & !OP20
# ci & !_LC3_D13 & !OP10 & OP20;
-- Node name is ':63'
-- Equation name is '_LC2_D10', type is buried
_LC2_D10 = LCELL( _EQ013);
_EQ013 = !ci & OP10 & !OP20
# !ci & !OP10 & OP20
# ci & OP10 & OP20
# ci & !OP10 & !OP20;
Project Information h:\pldshiyan\adder14\adder14.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,613K
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