📄 alpher2.rpt
字号:
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 0 18/0
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
132 - - - 26 OUTPUT 0 0 0 0 choice0
131 - - - 23 OUTPUT 0 0 0 0 choice1
130 - - - 22 OUTPUT 0 0 0 0 choice2
121 - - - 17 OUTPUT 0 0 0 0 choice3
137 - - - 30 OUTPUT 0 0 0 0 choice4
136 - - - 30 OUTPUT 0 0 0 0 choice5
135 - - - 29 OUTPUT 0 0 0 0 choice6
133 - - - 28 OUTPUT 0 0 0 0 choice7
138 - - - 31 OUTPUT 0 0 0 0 data0
10 - - B -- OUTPUT 0 1 0 0 data1
12 - - C -- OUTPUT 0 1 0 0 data2
13 - - C -- OUTPUT 0 0 0 0 data3
17 - - C -- OUTPUT 0 1 0 0 data4
140 - - - 32 OUTPUT 0 1 0 0 data5
8 - - A -- OUTPUT 0 1 0 0 data6
9 - - B -- OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 32 DFFE + 0 3 0 11 COUNT3 (:18)
- 5 - C 25 DFFE + 0 2 0 12 COUNT2 (:19)
- 4 - C 19 DFFE + 0 1 0 13 COUNT1 (:20)
- 8 - C 32 DFFE + 0 3 0 11 COUNT0 (:21)
- 7 - C 32 OR2 0 4 0 1 :201
- 2 - C 25 OR2 ! 0 4 1 2 :210
- 5 - C 32 OR2 ! 0 4 0 2 :222
- 3 - C 25 OR2 ! 0 4 0 2 :246
- 3 - C 19 OR2 0 4 1 0 :249
- 8 - C 25 AND2 0 3 0 1 :269
- 7 - C 25 OR2 0 4 1 0 :276
- 3 - C 32 OR2 0 4 0 2 :294
- 4 - C 32 OR2 0 3 1 0 :303
- 1 - C 25 OR2 s 0 4 0 2 ~327~1
- 4 - C 25 OR2 s 0 4 0 1 ~327~2
- 6 - C 25 OR2 0 4 1 0 :332
- 2 - C 32 AND2 s 0 3 0 2 ~411~1
- 6 - C 32 OR2 0 4 1 0 :411
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 3/144( 2%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: g:\pldshiyan\alpher2\alpher2.rpt
alpher2
** EQUATIONS **
clk : INPUT;
-- Node name is 'choice0'
-- Equation name is 'choice0', type is output
choice0 = VCC;
-- Node name is 'choice1'
-- Equation name is 'choice1', type is output
choice1 = VCC;
-- Node name is 'choice2'
-- Equation name is 'choice2', type is output
choice2 = VCC;
-- Node name is 'choice3'
-- Equation name is 'choice3', type is output
choice3 = VCC;
-- Node name is 'choice4'
-- Equation name is 'choice4', type is output
choice4 = VCC;
-- Node name is 'choice5'
-- Equation name is 'choice5', type is output
choice5 = VCC;
-- Node name is 'choice6'
-- Equation name is 'choice6', type is output
choice6 = VCC;
-- Node name is 'choice7'
-- Equation name is 'choice7', type is output
choice7 = VCC;
-- Node name is ':21' = 'COUNT0'
-- Equation name is 'COUNT0', location is LC8_C32, type is buried.
COUNT0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !COUNT0 & COUNT1
# !COUNT0 & COUNT2
# !COUNT0 & !COUNT3;
-- Node name is ':20' = 'COUNT1'
-- Equation name is 'COUNT1', location is LC4_C19, type is buried.
COUNT1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !COUNT0 & COUNT1
# COUNT0 & !COUNT1;
-- Node name is ':19' = 'COUNT2'
-- Equation name is 'COUNT2', location is LC5_C25, type is buried.
COUNT2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = COUNT0 & COUNT1 & !COUNT2
# !COUNT1 & COUNT2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -