t_butterworth_iir_biquad.v

基于butterworth的iir滤波器的verilog代码

`timescale 1ns/1ns

module t_butterworth_iir_biquad();
	
	parameter CLK_CYCLE = 20,
			  CLK_HCYCLE = 10;	// half clock cycle
	
	parameter INPUT_WIDTH = 18,
	          COEF_WIDTH = 10,
	          DLY_WIDTH = 18,
	          OUTPUT_WIDTH = 21,
	          FEEDBACK_WIDTH = 2 * DLY_WIDTH + 1;
		
	// input
	reg clk,clken;
	reg rst_n;
	reg [INPUT_WIDTH - 1:0] x;
	
	// output
	wire [OUTPUT_WIDTH-1:0] result;
   wire [FEEDBACK_WIDTH-1:0] feedback_fp;
   wire [DLY_WIDTH-1:0] wn, feedback;
		
	always #CLK_HCYCLE clk = ~clk;	// generate clock signal
	
	// Initialize Inputs
	initial
		begin
			clk = 1'b1;
			clken = 1'b0;
			rst_n = 1'b1;
			x = 18'd0;
			#CLK_CYCLE begin
			     rst_n = 1'b0;
			     clken = 1'b1;
			end
			#CLK_CYCLE  x = 18'd8;
			#CLK_CYCLE  x = 18'd3;
			#CLK_CYCLE  x = 18'd6;
			#CLK_CYCLE  x = 18'd15;
			#CLK_CYCLE  x = 18'd8;
			#CLK_CYCLE  x = 18'd0;
			
			#(20*CLK_CYCLE) $stop;
		end

	// ins
	butterworth_IIR_biquad  m1(
	    .reset(rst_n),
	    .clk(clk),
	    .clken(clken),
	    .x(x),
	    .result(result),
	    .feedback_fp(feedback_fp),
	    .feedback(feedback),
	    .wn(wn)
	    );
	
endmodule