poc1.rpt
来自「基于VHDL的POC编写与实现 实现三次握手」· RPT 代码 · 共 788 行 · 第 1/3 页
RPT
788 行
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\new\poc1.rpt
poc1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 IRQ
7 - - A -- OUTPUT 0 1 0 0 PD0
33 - - F -- OUTPUT 0 1 0 0 PD1
30 - - F -- OUTPUT 0 1 0 0 PD2
31 - - F -- OUTPUT 0 1 0 0 PD3
78 - - F -- OUTPUT 0 1 0 0 PD4
29 - - E -- OUTPUT 0 1 0 0 PD5
28 - - E -- OUTPUT 0 1 0 0 PD6
27 - - E -- OUTPUT 0 1 0 0 PD7
100 - - A -- OUTPUT 0 1 0 0 TR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\new\poc1.rpt
poc1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 30 DFFE + 1 1 0 1 state~1
- 6 - A 30 OR2 s ! 1 1 0 1 state~2~2
- 4 - A 30 DFFE + 1 1 0 4 state~2
- 3 - A 30 DFFE + 1 2 0 7 state~3
- 3 - E 19 DFFE + 1 2 1 0 :16
- 5 - E 19 DFFE + 1 2 1 0 :18
- 7 - E 19 DFFE + 1 2 1 0 :20
- 8 - F 26 DFFE + 1 2 1 0 :22
- 3 - F 26 DFFE + 1 2 1 0 :24
- 1 - F 26 DFFE + 1 2 1 0 :26
- 6 - F 26 DFFE + 1 2 1 0 :28
- 5 - A 30 DFFE + 1 2 1 0 :30
- 7 - A 27 DFFE + 1 2 1 0 :32
- 7 - A 30 DFFE + 1 2 1 0 :34
- 6 - A 27 DFFE + ! 0 3 0 2 SR7 (:36)
- 4 - A 27 DFFE + 1 2 0 1 SR0 (:43)
- 4 - E 19 DFFE + 2 1 0 1 BR7 (:44)
- 2 - E 19 DFFE + 2 1 0 1 BR6 (:45)
- 1 - E 19 DFFE + 2 1 0 1 BR5 (:46)
- 7 - F 26 DFFE + 2 1 0 1 BR4 (:47)
- 5 - F 26 DFFE + 2 1 0 1 BR3 (:48)
- 4 - F 26 DFFE + 2 1 0 1 BR2 (:49)
- 2 - F 26 DFFE + 2 1 0 1 BR1 (:50)
- 8 - A 30 DFFE + 2 1 0 1 BR0 (:51)
- 2 - A 27 OR2 ! 4 0 0 2 :163
- 1 - A 27 AND2 4 0 0 4 :293
- 1 - A 30 OR2 s 1 2 0 8 ~807~1
- 5 - A 27 OR2 s ! 1 3 0 1 ~825~1
- 8 - A 27 AND2 0 4 0 1 :898
- 1 - A 28 AND2 s ! 0 2 0 9 ~969~1
- 3 - A 27 OR2 ! 0 2 0 2 :972
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\new\poc1.rpt
poc1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/144( 5%) 0/ 72( 0%) 3/ 72( 4%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 4/144( 2%) 0/ 72( 0%) 3/ 72( 4%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
F: 8/144( 5%) 0/ 72( 0%) 2/ 72( 2%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\new\poc1.rpt
poc1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 23 CLK
Device-Specific Information: d:\new\poc1.rpt
poc1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 23 CS
Device-Specific Information: d:\new\poc1.rpt
poc1
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
RDY : INPUT;
RW : INPUT;
-- Node name is ':51' = 'BR0'
-- Equation name is 'BR0', location is LC8_A30, type is buried.
BR0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, CS);
_EQ001 = BR0 & _LC1_A28
# D0 & !_LC1_A28;
-- Node name is ':50' = 'BR1'
-- Equation name is 'BR1', location is LC2_F26, type is buried.
BR1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, CS);
_EQ002 = BR1 & _LC1_A28
# D1 & !_LC1_A28;
-- Node name is ':49' = 'BR2'
-- Equation name is 'BR2', location is LC4_F26, type is buried.
BR2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, CS);
_EQ003 = BR2 & _LC1_A28
# D2 & !_LC1_A28;
-- Node name is ':48' = 'BR3'
-- Equation name is 'BR3', location is LC5_F26, type is buried.
BR3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, CS);
_EQ004 = BR3 & _LC1_A28
# D3 & !_LC1_A28;
-- Node name is ':47' = 'BR4'
-- Equation name is 'BR4', location is LC7_F26, type is buried.
BR4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, CS);
_EQ005 = BR4 & _LC1_A28
# D4 & !_LC1_A28;
-- Node name is ':46' = 'BR5'
-- Equation name is 'BR5', location is LC1_E19, type is buried.
BR5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, CS);
_EQ006 = BR5 & _LC1_A28
# D5 & !_LC1_A28;
-- Node name is ':45' = 'BR6'
-- Equation name is 'BR6', location is LC2_E19, type is buried.
BR6 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, CS);
_EQ007 = BR6 & _LC1_A28
# D6 & !_LC1_A28;
-- Node name is ':44' = 'BR7'
-- Equation name is 'BR7', location is LC4_E19, type is buried.
BR7 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, CS);
_EQ008 = BR7 & _LC1_A28
# D7 & !_LC1_A28;
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = _LC7_A27;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = _LC5_A30;
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = _LC6_F26;
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = _LC1_F26;
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = _LC3_F26;
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = _LC8_F26;
-- Node name is 'PD5'
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