poc1.rpt

来自「基于VHDL的POC编写与实现 实现三次握手」· RPT 代码 · 共 788 行 · 第 1/3 页

-- Equation name is 'PD5', type is output 
PD5      =  _LC7_E19;

-- Node name is 'PD6' 
-- Equation name is 'PD6', type is output 
PD6      =  _LC5_E19;

-- Node name is 'PD7' 
-- Equation name is 'PD7', type is output 
PD7      =  _LC3_E19;

-- Node name is ':43' = 'SR0' 
-- Equation name is 'SR0', location is LC4_A27, type is buried.
SR0      = DFFE( _EQ009, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ009 =  D0 &  _LC2_A27 &  _LC3_A27
         # !_LC2_A27 &  SR0
         # !_LC3_A27 &  SR0;

-- Node name is ':36' = 'SR7' 
-- Equation name is 'SR7', location is LC6_A27, type is buried.
!SR7     = SR7~NOT;
SR7~NOT  = DFFE( _EQ010, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ010 = !_LC5_A27 & !state~3
         # !_LC5_A27 & !_LC6_A30 & !SR7;

-- Node name is 'state~1' 
-- Equation name is 'state~1', location is LC2_A30, type is buried.
state~1  = DFFE( _EQ011, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ011 = !RDY &  state~2
         # !RDY &  state~1;

-- Node name is 'state~2~2' 
-- Equation name is 'state~2~2', location is LC6_A30, type is buried.
-- synthesized logic cell 
!_LC6_A30 = _LC6_A30~NOT;
_LC6_A30~NOT = LCELL( _EQ012);
  _EQ012 =  state~2
         # !RDY;

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC4_A30, type is buried.
state~2  = DFFE( _EQ013, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ013 = !_LC1_A28
         #  RDY &  state~2;

-- Node name is 'state~3' 
-- Equation name is 'state~3', location is LC3_A30, type is buried.
state~3  = DFFE( _EQ014, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ014 = !RDY &  state~3
         #  _LC1_A27 & !RDY
         # !state~1 &  state~3
         #  _LC1_A27 & !state~1;

-- Node name is 'TR' 
-- Equation name is 'TR', type is output 
TR       =  _LC7_A30;

-- Node name is ':16' 
-- Equation name is '_LC3_E19', type is buried 
_LC3_E19 = DFFE( _EQ015, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ015 =  BR7 & !_LC1_A30
         #  _LC1_A30 &  _LC3_E19;

-- Node name is ':18' 
-- Equation name is '_LC5_E19', type is buried 
_LC5_E19 = DFFE( _EQ016, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ016 =  BR6 & !_LC1_A30
         #  _LC1_A30 &  _LC5_E19;

-- Node name is ':20' 
-- Equation name is '_LC7_E19', type is buried 
_LC7_E19 = DFFE( _EQ017, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ017 =  BR5 & !_LC1_A30
         #  _LC1_A30 &  _LC7_E19;

-- Node name is ':22' 
-- Equation name is '_LC8_F26', type is buried 
_LC8_F26 = DFFE( _EQ018, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ018 =  BR4 & !_LC1_A30
         #  _LC1_A30 &  _LC8_F26;

-- Node name is ':24' 
-- Equation name is '_LC3_F26', type is buried 
_LC3_F26 = DFFE( _EQ019, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ019 =  BR3 & !_LC1_A30
         #  _LC1_A30 &  _LC3_F26;

-- Node name is ':26' 
-- Equation name is '_LC1_F26', type is buried 
_LC1_F26 = DFFE( _EQ020, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ020 =  BR2 & !_LC1_A30
         #  _LC1_A30 &  _LC1_F26;

-- Node name is ':28' 
-- Equation name is '_LC6_F26', type is buried 
_LC6_F26 = DFFE( _EQ021, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ021 =  BR1 & !_LC1_A30
         #  _LC1_A30 &  _LC6_F26;

-- Node name is ':30' 
-- Equation name is '_LC5_A30', type is buried 
_LC5_A30 = DFFE( _EQ022, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ022 =  BR0 & !_LC1_A30
         #  _LC1_A30 &  _LC5_A30;

-- Node name is ':32' 
-- Equation name is '_LC7_A27', type is buried 
_LC7_A27 = DFFE( _EQ023, GLOBAL( CLK),  VCC,  VCC,  CS);
  _EQ023 =  _LC8_A27
         #  _LC7_A27 &  state~3;

-- Node name is ':34' 
-- Equation name is '_LC7_A30', type is buried 
_LC7_A30 = DFFE( _EQ024, GLOBAL( CLK), GLOBAL( CS),  VCC,  VCC);
  _EQ024 =  _LC7_A30 & !state~3
         #  _LC7_A30 & !state~2
         #  RDY &  state~2 &  state~3;

-- Node name is ':163' 
-- Equation name is '_LC2_A27', type is buried 
!_LC2_A27 = _LC2_A27~NOT;
_LC2_A27~NOT = LCELL( _EQ025);
  _EQ025 =  A1
         # !RW
         #  A2
         #  A0;

-- Node name is ':293' 
-- Equation name is '_LC1_A27', type is buried 
_LC1_A27 = LCELL( _EQ026);
  _EQ026 =  A0 & !A1 & !A2 &  RW;

-- Node name is '~807~1' 
-- Equation name is '~807~1', location is LC1_A30, type is buried.
-- synthesized logic cell 
_LC1_A30 = LCELL( _EQ027);
  _EQ027 =  state~2
         #  RDY
         # !state~3;

-- Node name is '~825~1' 
-- Equation name is '~825~1', location is LC5_A27, type is buried.
-- synthesized logic cell 
!_LC5_A27 = _LC5_A27~NOT;
_LC5_A27~NOT = LCELL( _EQ028);
  _EQ028 = !D7 & !SR7
         # !D7 &  _LC2_A27
         # !_LC2_A27 & !SR7
         # !_LC3_A27;

-- Node name is ':898' 
-- Equation name is '_LC8_A27', type is buried 
_LC8_A27 = LCELL( _EQ029);
  _EQ029 = !_LC1_A27 &  SR0 &  SR7 & !state~3;

-- Node name is '~969~1' 
-- Equation name is '~969~1', location is LC1_A28, type is buried.
-- synthesized logic cell 
!_LC1_A28 = _LC1_A28~NOT;
_LC1_A28~NOT = LCELL( _EQ030);
  _EQ030 =  _LC1_A27 & !state~3;

-- Node name is ':972' 
-- Equation name is '_LC3_A27', type is buried 
!_LC3_A27 = _LC3_A27~NOT;
_LC3_A27~NOT = LCELL( _EQ031);
  _EQ031 =  state~3
         #  _LC1_A27;



Project Information                                            d:\new\poc1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,175K