fir_parall_v1.v

基于verilog的fir滤波器设计

`define IDATA_WIDTH		16	// input data width
`define PDATA_WIDTH  	17	// process data width
`define FIR_TAP  		11	// fir tap
`define FIR_TAPHALF  	6	// fir tap half
`define COEFF_WIDTH  	8	// coff width
`define OUT_WIDTH  		28	// output width


module fir_parall_v1(clk,rst_n,fir_in,fir_out);
	
	
	parameter cof0 = `COEFF_WIDTH'd3,
			  cof1 = `COEFF_WIDTH'd16,
			  cof2 = `COEFF_WIDTH'd43,
			  cof3 = `COEFF_WIDTH'd80,
			  cof4 = `COEFF_WIDTH'd113,
			  cof5 = `COEFF_WIDTH'd127;
	
	input   clk;
	input   rst_n;
	input  [`IDATA_WIDTH - 1:0] fir_in;
	output [`OUT_WIDTH - 1:0]   fir_out;
	
	// test
	//output [IDATA_WIDTH - 1:0] fir_out1;
	
	reg [`OUT_WIDTH - 1:0] fir_out;
	
	reg [`IDATA_WIDTH - 1:0] fir_in_reg;
	reg [`PDATA_WIDTH - 1:0] shift_buf [`FIR_TAP - 1:0];	// define 8 shift buffer
	
	reg [`PDATA_WIDTH - 1:0] add0;
	reg [`PDATA_WIDTH - 1:0] add1;
	reg [`PDATA_WIDTH - 1:0] add2;
	reg [`PDATA_WIDTH - 1:0] add3;
	reg [`PDATA_WIDTH - 1:0] add4;
	reg [`PDATA_WIDTH - 1:0] add5;
	
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul0;
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul1;
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul2;
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul3;
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul4;
	wire [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul5;
	
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul0_reg;
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul1_reg;
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul2_reg;
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul3_reg;
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul4_reg;
	reg [`PDATA_WIDTH + `COEFF_WIDTH - 1:0] mul5_reg;
	
	reg [`PDATA_WIDTH + `COEFF_WIDTH:0] add_mul0;
	reg [`PDATA_WIDTH + `COEFF_WIDTH:0] add_mul1;
	reg [`PDATA_WIDTH + `COEFF_WIDTH:0] add_mul2;
	
	integer i,j;
	
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			fir_in_reg <= `IDATA_WIDTH'b0;
		else
			fir_in_reg <= fir_in;
	end
	
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			for (i=0; i<=`FIR_TAP-1; i=i+1)
				shift_buf[i] <= `PDATA_WIDTH'b0;
		else begin
			for (j=0; j<`FIR_TAP-1; j=j+1)
				shift_buf[j+1] <= shift_buf[j];
			shift_buf[0] <= {fir_in_reg[`IDATA_WIDTH - 1],fir_in_reg}; // sign expand
		end
	end
	
	// added pipeline1
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n) begin
			add0 <= `PDATA_WIDTH'b0;
			add1 <= `PDATA_WIDTH'b0;
			add2 <= `PDATA_WIDTH'b0;
			add3 <= `PDATA_WIDTH'b0;
			add4 <= `PDATA_WIDTH'b0;
			add5 <= `PDATA_WIDTH'b0;
		end
		else begin
			add0 <= shift_buf[0] + shift_buf[10];
			add1 <= shift_buf[1] + shift_buf[9];
			add2 <= shift_buf[2] + shift_buf[8];
			add3 <= shift_buf[3] + shift_buf[7];
			add4 <= shift_buf[4] + shift_buf[6];
			add5 <= shift_buf[5];
		end
	end
	
	lpm_mult mult_0	// Multiply cof0*add0 = mul0
		(.dataa(cof0),.datab(add0),.result(mul0),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_0.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_0.lpm_widtha = `COEFF_WIDTH,
				 mult_0.lpm_widthb = `PDATA_WIDTH,
				 mult_0.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_0.lpm_widths = 1,
				 mult_0.lpm_pipeline = 0,
				 mult_0.lpm_representation = "SIGNED";
	
	lpm_mult mult_1	// Multiply cof1*add1 = mul1
		(.dataa(cof1),.datab(add1),.result(mul1),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_1.lpm_widtha = `COEFF_WIDTH,
				 mult_1.lpm_widthb = `PDATA_WIDTH,
				 mult_1.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_1.lpm_widths = 1,
				 mult_1.lpm_pipeline = 0,
				 mult_1.lpm_representation = "SIGNED";
	
	lpm_mult mult_2	// Multiply cof2*add2 = mul2
		(.dataa(cof2),.datab(add2),.result(mul2),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_2.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_2.lpm_widtha = `COEFF_WIDTH,
				 mult_2.lpm_widthb = `PDATA_WIDTH,
				 mult_2.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_2.lpm_widths = 1,
				 mult_2.lpm_pipeline = 0,
				 mult_2.lpm_representation = "SIGNED";

	lpm_mult mult_3	// Multiply cof3*add3 = mul3
		(.dataa(cof3),.datab(add3),.result(mul3),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_3.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_3.lpm_widtha = `COEFF_WIDTH,
				 mult_3.lpm_widthb = `PDATA_WIDTH,
				 mult_3.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_3.lpm_widths = 1,
				 mult_3.lpm_pipeline = 0,
				 mult_3.lpm_representation = "SIGNED";
	
	lpm_mult mult_4	// Multiply cof4*add4 = mul4
		(.dataa(cof4),.datab(add4),.result(mul4),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_4.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_4.lpm_widtha = `COEFF_WIDTH,
				 mult_4.lpm_widthb = `PDATA_WIDTH,
				 mult_4.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_4.lpm_widths = 1,
				 mult_4.lpm_pipeline = 0,
				 mult_4.lpm_representation = "SIGNED";
				
	lpm_mult mult_5	// Multiply cof5*add5 = mul5
		(.dataa(cof5),.datab(add5),.result(mul5),
		 .sum(1'b0),.clken(1'b0),.aclr(1'b0));
		defparam mult_5.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
				 mult_5.lpm_widtha = `COEFF_WIDTH,
				 mult_5.lpm_widthb = `PDATA_WIDTH,
				 mult_5.lpm_widthp = `COEFF_WIDTH + `PDATA_WIDTH,
				 mult_5.lpm_widths = 1,
				 mult_5.lpm_pipeline = 0,
				 mult_5.lpm_representation = "SIGNED";
	
	// added pipeline2
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n) begin
			mul0_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
			mul1_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
			mul2_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
			mul3_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
			mul4_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
			mul5_reg <= `PDATA_WIDTH+`COEFF_WIDTH'b0;
		end			
		else begin
			mul0_reg <= mul0;
			mul1_reg <= mul1;
			mul2_reg <= mul2;
			mul3_reg <= mul3;
			mul4_reg <= mul4;
			mul5_reg <= mul5;
		end
	end
	
	// added pipeline3
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n) begin
			add_mul0 <= `PDATA_WIDTH+`COEFF_WIDTH+1'b0;
			add_mul1 <= `PDATA_WIDTH+`COEFF_WIDTH+1'b0;
			add_mul2 <= `PDATA_WIDTH+`COEFF_WIDTH+1'b0;
		end			
		else begin
			add_mul0 <= {mul0_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul0_reg} 
					+ {mul1_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul1_reg};
			add_mul1 <= {mul2_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul2_reg} 
					+ {mul3_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul3_reg};
			add_mul2 <= {mul4_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul4_reg} 
					+ {mul5_reg[`PDATA_WIDTH+`COEFF_WIDTH-1],mul5_reg};
		end
	end
	
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			fir_out <= `PDATA_WIDTH+`COEFF_WIDTH+3'b0;
		else
			fir_out <= 
			{add_mul0[`PDATA_WIDTH+`COEFF_WIDTH],add_mul0[`PDATA_WIDTH+`COEFF_WIDTH],add_mul0}
		+ {add_mul1[`PDATA_WIDTH+`COEFF_WIDTH],add_mul1[`PDATA_WIDTH+`COEFF_WIDTH],add_mul1}
		+ {add_mul2[`PDATA_WIDTH+`COEFF_WIDTH],add_mul2[`PDATA_WIDTH+`COEFF_WIDTH],add_mul2};
	end
	
endmodule