max3490.tan.rpt

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· RPT 代码 · 共 289 行 · 第 1/5 页

; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                ; To                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 179.73 MHz ( period = 5.564 ns )                    ; counter4[8]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 5.291 ns                ;
; N/A                                     ; 181.09 MHz ( period = 5.522 ns )                    ; rs232tx:m2|prescaler_count_l[0]     ; rs232tx:m2|m1_state.m1_sending              ; clk        ; clk      ; None                        ; None                      ; 5.252 ns                ;
; N/A                                     ; 185.22 MHz ( period = 5.399 ns )                    ; counter4[0]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 5.126 ns                ;
; N/A                                     ; 185.29 MHz ( period = 5.397 ns )                    ; counter4[10]                        ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 5.124 ns                ;
; N/A                                     ; 187.48 MHz ( period = 5.334 ns )                    ; rs232tx:m2|prescaler_count_l[2]     ; rs232tx:m2|m1_state.m1_sending              ; clk        ; clk      ; None                        ; None                      ; 5.064 ns                ;
; N/A                                     ; 188.68 MHz ( period = 5.300 ns )                    ; counter4[6]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; counter4[8]                         ; state.MAX3490_idle                          ; clk        ; clk      ; None                        ; None                      ; 5.010 ns                ;
; N/A                                     ; 189.57 MHz ( period = 5.275 ns )                    ; counter4[9]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 5.002 ns                ;
; N/A                                     ; 190.88 MHz ( period = 5.239 ns )                    ; rs232tx:m2|prescaler_count_l[3]     ; rs232tx:m2|m1_state.m1_sending              ; clk        ; clk      ; None                        ; None                      ; 4.969 ns                ;
; N/A                                     ; 191.53 MHz ( period = 5.221 ns )                    ; rs232tx:m2|prescaler_count_l[0]     ; rs232tx:m2|tx_bit_count_l[1]                ; clk        ; clk      ; None                        ; None                      ; 4.951 ns                ;
; N/A                                     ; 191.57 MHz ( period = 5.220 ns )                    ; rs232tx:m2|prescaler_count_l[0]     ; rs232tx:m2|tx_bit_count_l[2]                ; clk        ; clk      ; None                        ; None                      ; 4.950 ns                ;
; N/A                                     ; 191.68 MHz ( period = 5.217 ns )                    ; rs232tx:m2|prescaler_count_l[0]     ; rs232tx:m2|tx_bit_count_l[0]                ; clk        ; clk      ; None                        ; None                      ; 4.947 ns                ;
; N/A                                     ; 191.72 MHz ( period = 5.216 ns )                    ; rs232tx:m2|prescaler_count_l[0]     ; rs232tx:m2|tx_bit_count_l[3]                ; clk        ; clk      ; None                        ; None                      ; 4.946 ns                ;
; N/A                                     ; 191.79 MHz ( period = 5.214 ns )                    ; counter4[1]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 4.941 ns                ;
; N/A                                     ; 195.39 MHz ( period = 5.118 ns )                    ; counter4[0]                         ; state.MAX3490_idle                          ; clk        ; clk      ; None                        ; None                      ; 4.845 ns                ;
; N/A                                     ; 195.47 MHz ( period = 5.116 ns )                    ; counter4[10]                        ; state.MAX3490_idle                          ; clk        ; clk      ; None                        ; None                      ; 4.843 ns                ;
; N/A                                     ; 195.69 MHz ( period = 5.110 ns )                    ; counter4[3]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 4.837 ns                ;
; N/A                                     ; 195.96 MHz ( period = 5.103 ns )                    ; counter4[4]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 4.830 ns                ;
; N/A                                     ; 196.27 MHz ( period = 5.095 ns )                    ; rs232tx:m2|m1_state.m1_waiting      ; rs232tx:m2|tx_bit_count_l[1]                ; clk        ; clk      ; None                        ; None                      ; 4.823 ns                ;
; N/A                                     ; 196.31 MHz ( period = 5.094 ns )                    ; rs232tx:m2|m1_state.m1_waiting      ; rs232tx:m2|tx_bit_count_l[2]                ; clk        ; clk      ; None                        ; None                      ; 4.822 ns                ;
; N/A                                     ; 196.35 MHz ( period = 5.093 ns )                    ; counter4[15]                        ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 4.820 ns                ;
; N/A                                     ; 196.43 MHz ( period = 5.091 ns )                    ; rs232tx:m2|m1_state.m1_waiting      ; rs232tx:m2|tx_bit_count_l[0]                ; clk        ; clk      ; None                        ; None                      ; 4.819 ns                ;
; N/A                                     ; 196.46 MHz ( period = 5.090 ns )                    ; rs232tx:m2|m1_state.m1_waiting      ; rs232tx:m2|tx_bit_count_l[3]                ; clk        ; clk      ; None                        ; None                      ; 4.818 ns                ;
; N/A                                     ; 196.89 MHz ( period = 5.079 ns )                    ; counter4[2]                         ; state.MAX3490_start                         ; clk        ; clk      ; None                        ; None                      ; 4.806 ns                ;