prev_cmp_select_32.map.qmsg

32位 2选1 选择器 VHDL语言程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 07 11:48:54 2008 " "Info: Processing started: Sun Dec 07 11:48:54 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off select_32 -c select_32 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off select_32 -c select_32" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "select_32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file select_32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 select_32-bevi " "Info: Found design unit 1: select_32-bevi" {  } { { "select_32.vhd" "" { Text "D:/cpld/select_32/select_32.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 select_32 " "Info: Found entity 1: select_32" {  } { { "select_32.vhd" "" { Text "D:/cpld/select_32/select_32.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_READ_FROM_OUT" "Y select_32.vhd(13) " "Error (10309): VHDL Interface Declaration error in select_32.vhd(13): interface object \"Y\" of mode out cannot be read. Change object mode to buffer." {  } { { "select_32.vhd" "" { Text "D:/cpld/select_32/select_32.vhd" 13 0 0 } }  } 0 10309 "VHDL Interface Declaration error in %2!s!: interface object \"%1!s!\" of mode out cannot be read. Change object mode to buffer." 0 0 "" 0}
{ "Error" "EVRFX_VHDL_NO_UNIQUE_OPER_DEFN_MATCH" "0 \"<=\" select_32.vhd(13) " "Error (10327): VHDL error at select_32.vhd(13): can't determine definition of operator \"\"<=\"\" -- found 0 possible definitions" {  } { { "select_32.vhd" "" { Text "D:/cpld/select_32/select_32.vhd" 13 0 0 } }  } 0 10327 "VHDL error at %3!s!: can't determine definition of operator \"%2!s!\" -- found %1!d! possible definitions" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Dec 07 11:48:56 2008 " "Error: Processing ended: Sun Dec 07 11:48:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}