test.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:59:36 01/21/2007
// Design Name:   top_top
// Module Name:   test.v
// Project Name:  dfadg
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_v;

	// Inputs
	reg [3:0] floor_address;
	reg up_user1;
	reg down_user1;
	reg up_user2;
	reg down_user2;
	reg [5:0] address_user1;
	reg [5:0] address_user2;
	reg start1;
	reg address_ok1;
	reg start2;
	reg address_ok2;
	reg reset;
	reg clk;

	// Outputs
	wire [3:0] cur_lift1_1;
	wire [3:0] cur_lift1_2;
	wire [3:0] cur_lift2_1;
	wire [3:0] cur_lift2_2;
	wire [1:0] state1_1;
	wire [1:0] state1_2;
	wire [1:0] state2_1;
	wire [1:0] state2_2;

	// Instantiate the Unit Under Test (UUT)
	top_top uut (
		.cur_lift1_1(cur_lift1_1), 
		.cur_lift1_2(cur_lift1_2), 
		.cur_lift2_1(cur_lift2_1), 
		.cur_lift2_2(cur_lift2_2), 
		.state1_1(state1_1), 
		.state1_2(state1_2), 
		.state2_1(state2_1), 
		.state2_2(state2_2), 
		.floor_address(floor_address), 
		.up_user1(up_user1), 
		.down_user1(down_user1), 
		.up_user2(up_user2), 
		.down_user2(down_user2), 
		.address_user1(address_user1), 
		.address_user2(address_user2), 
		.start1(start1), 
		.address_ok1(address_ok1), 
		.start2(start2), 
		.address_ok2(address_ok2), 
		.reset(reset), 
		.clk(clk)
	);

	initial begin
		// Initialize Inputs
		floor_address = 7;
		up_user1 = 1;
		down_user1 = 1;
		address_user1 = 'h1F;
		start1 = 1;
		address_ok1 = 1;
		up_user2 = 1;
		down_user2 = 1;
		address_user2 = 'h0F;
		start2 = 1;
		address_ok2 = 1;
		reset = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;  
		// Add stimulus here
		 #220  up_user1 = 0;
		 # 200 up_user1 = 1;
       #5000 $stop();
		 address_user1 = 'h1A;
		 address_ok1 = 0;
		 #100 address_ok1 = 1;
		 #100
		 address_user1 = 'h1E;
		 address_ok1 = 0;
		 #100 address_ok1 = 1;
		 #50 start1 = 0;
		 #100 start1 = 1;
		 #5000 $stop();
		 #500 $stop();
		 floor_address1 = 6;
		#220  up_user1 = 0;
		 # 200 up_user1 = 1;
		 #5000$stop();
      initial begin
		// Initialize Inputs
		floor_address = 9;
		up_user1 = 1;
		down_user1 = 1;
		address_user1 = 'h1F;
		start1 = 1;
		address_ok1 = 1;
		up_user2 = 1;
		down_user2 = 1;
		address_user2 = 'h0F;
		start2 = 1;
		address_ok2 = 1;
		reset = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;  
		// Add stimulus here
		 #220  up_user2 = 0;
		 # 200 up_user2 = 1;
       #5000 $stop();
		 address_user2 = 'h1A;
		 address_ok2 = 0;
		 #100 address_ok2 = 1;
		 #100
		 address_user2 = 'h1E;
		 address_ok2 = 0;
		 #100 address_ok2 = 1;
		 #50 start2 = 0;
		 #100 start2 = 1;
		 #5000 $stop();
		 #500 $stop();
		 floor_address2 = 6;
		#220  up_user2 = 0;
		 # 200 up_user2 = 1;
		 #5000$stop();


         end
      always # 20 clk = ~clk;
endmodule