top.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    07:53:41 01/08/07
// Design Name:    
// Module Name:    top
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module top(cur_lift1,cur_lift2,state1,state2,same_in,OK,floor_address,up_user,down_user,
           address_user,start,address_ok,same_out,reset,clk);

input  up_user,down_user,start,address_ok,reset,clk;
input [1:0] same_out;
input	[3:0]	floor_address;
input [5:0] address_user;

output OK;
output [1:0]same_in,state2,state1;
output [3:0] cur_lift1, cur_lift2;

wire [23:0]  lift1_out,lift2_out ;
wire  RELE,DESLE1,DESLE2;

wire[7:0] floor_out0;		
wire[7:0] floor_out1;  
wire[7:0] floor_out2;	
wire[7:0] floor_out3;	
wire[7:0] floor_out4;	
wire[7:0] floor_out5;		
wire[7:0] floor_out6;	
wire[7:0] floor_out7;	
wire[7:0] floor_out8;	
wire[7:0] floor_out9;	
wire[7:0] floor_out10;
wire[7:0] floor_out11;
wire[7:0] floor_out12;
wire[7:0] floor_out13;	
wire[7:0] floor_out14;	
wire[7:0] floor_out15;
wire[7:0] request_in;
wire[7:0] request_out;

wire [3:0] address_user1,address_user2;
wire up_slect,down_slect,start_slect,address_ok_slect,
     start_share1,start_share2,address_ok_share1,address_ok_share2;

wire[2:0] DDR_out	;
wire [1:0] best_lift,buzy2a1;

assign  cur_lift1 = lift1_out[19:16];
assign  cur_lift2 = lift2_out[19:16];
assign same_in	= {lift1_out[22],~lift1_out[23]&~lift2_out[23]&
                 (lift1_out[22]&lift2_out[22]|~lift1_out[22]&~lift2_out[22])};
assign buzy2a1	= {~lift2_out[23],~lift1_out[23]};



deal_user_in deal_in(.up_slect(up_slect),.down_slect(down_slect),.start_slect(start_slect),
     .address_ok_slect(address_ok_slect),
     .up(up_user),.down(down_user),.start(start),.address_ok(address_ok),.reset(reset),.clk(clk));

share_input share_in(.start_share1(start_share1),.address_user1(address_user1),.address_ok_share1(address_ok_share1),
     .start_share2(start_share2),.address_user2(address_user2),.address_ok_share2(address_ok_share2),
	  .start_slect(start_slect),.address_user(address_user[3:0]),.address_ok_slect(address_ok_slect),.address_user_h(address_user[5:4]));

lift_top lift1 (.lift_out(lift1_out),.state(state1),.request(request_out),.address_user(address_user1),
	            .DESLE(DESLE1),.start(start_share1),.address_ok(address_ok_share1),.clk(clk),.reset(reset));

lift_top lift2 (.lift_out(lift2_out),.state(state2),.request(request_out),.address_user(address_user2),
	            .DESLE(DESLE2),.start(start_share2),.address_ok(address_ok_share2),.clk(clk),.reset(reset));

floor floors (.floor_out0(floor_out0),.floor_out1(floor_out1),.floor_out2(floor_out2),.floor_out3(floor_out3),
              .floor_out4(floor_out4),.floor_out5(floor_out5),.floor_out6(floor_out6),.floor_out7(floor_out7),
              .floor_out8(floor_out8),.floor_out9(floor_out9),.floor_out10(floor_out10),.floor_out11(floor_out11),
				  .floor_out12(floor_out12),.floor_out13(floor_out13),.floor_out14(floor_out14),.floor_out15(floor_out15),
				  .floor_address(floor_address),.up(up_slect),.down(down_slect),.clk(clk),.reset(reset));
or16 or16(.in_0(floor_out0),.in_1(floor_out1),.in_2(floor_out2),.in_3(floor_out3),.in_4(floor_out4),
          .in_5(floor_out5),.in_6(floor_out6),.in_7(floor_out7),.in_8(floor_out8),.in_9(floor_out9),
			 .in_10(floor_out10),.in_11(floor_out11),.in_12(floor_out12),.in_13(floor_out13),.in_14(floor_out14),
			 .in_15(floor_out15),.out(request_in));
register #(8) request (.register_out(request_out),.register_in(request_in),.clk(clk),.reset(reset),.load_enable(RELE));

search DD (.request_floor({request_out[7:4],request_out[1]}),.lift_1(lift1_out),.lift_2(lift2_out),
           .best_lift(best_lift),.enable(anwser));
register #(3) DDR (.register_out(DDR_out),.register_in({anwser,best_lift}),.clk(clk),.reset(reset),.load_enable(DDRLE));


CU CU(.request(request_out[1:0]),.same_in(buzy2a1), .same_out(same_out),.result(DDR_out),.RELE(RELE),.DDRLE(DDRLE),
      .DESLE1(DESLE1),.DESLE2(DESLE2),
		.OK(OK),.clk(clk),.reset(reset));
endmodule