cu.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:08:46 12/19/06
// Design Name:    
// Module Name:    CU
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module CU(request,same_in,same_out,result,RELE,DDRLE,DESLE1,
          DESLE2,OK,clk,reset);
input  [1:0] request;
input  [1:0] same_in,same_out;  
input  [2:0] result;
input clk,reset;


output RELE,DDRLE,DESLE1,DESLE2,OK;
reg  RELE,DDRLE,DESLE1,DESLE2,OK;

wire  result1;
assign result1 = (result == 2)? 1:0;
parameter FIRST = 'b00, SECOND = 'b01,THIRD = 'b10, FORTH = 'b11,FIFTH = 'b100;

reg [2:0] state ;//,next_state;

always @  (posedge clk or negedge reset)
begin
 if(!reset)  
		 state  <= FIRST ;
  else
	case(state)
	  FIRST:begin  
	        if(request != 0) begin state <=SECOND; 	end
	          else state  <= FIRST; 
			  end

	  SECOND:  begin	 state  <= THIRD; end

	  THIRD:	 begin 
	          if(result[2] == 0)	state  <= FIFTH; 
	           else  if (same_in[result1+1] ==1 &&same_out[0] ==1 && request[same_out[1]]) state  <= FIFTH; 
				   else 	  state  <= FORTH; 
				 end

	  FORTH:	begin  state  <= FIFTH;  end
	  FIFTH:	begin  state  <= FIRST;  end
	  default  begin  state  <= FIRST;  end
	endcase
end

always @  (state or result or  request)
begin
DDRLE='b0; //保存调度结果=1，（处理完后=0；	 保留一拍即可 ）
OK=0;     // 当成功时=1；
DESLE1 = 0;// =1时将FLOOR中的ADDRES 指向的电梯置1；
DESLE2 = 0;// =1时将FLOOR中的ADDRES 指向的电梯置1；


case(state)

  FIRST: begin   if(request != 0)  RELE = 0;	else RELE = 1;end

  SECOND:	begin  DDRLE =1; end

  THIRD:	  ;

  FORTH:	begin case(result[1:0]) 
     
         'b01:begin DESLE1=1;OK=1	;end 
			'b10:begin DESLE2=1;OK=1	;end  
			 endcase	 end
  FIFTH:  RELE =1;
  default 	; 

endcase
end


endmodule