top_top.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:56:05 01/12/07
// Design Name:    
// Module Name:    top_top
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module top_top(cur_lift1_1, cur_lift1_2,cur_lift2_1, cur_lift2_2,state1_1,state1_2,state2_1,state2_2, 
               floor_address,up_user1,down_user1,up_user2,down_user2,address_user1, address_user2,start1,
					address_ok1,start2,address_ok2,reset,clk);

output [3:0] cur_lift1_1, cur_lift1_2, cur_lift2_1, cur_lift2_2;
output [1:0] state1_1,state1_2,state2_1,state2_2;

input  up_user1,down_user1,up_user2,down_user2,start1,address_ok1,start2,address_ok2,reset,clk;

input	[3:0]	floor_address;
input [5:0] address_user1, address_user2;


wire[1:0]same_in1,same_in2;

top  part1(.cur_lift1(cur_lift1_1),.cur_lift2(cur_lift1_2),.state1(state1_1),.state2(state1_2),.same_in(same_in1),.OK(),
           .floor_address(floor_address),.up_user(up_user1),.down_user(down_user1),
           .address_user(address_user1),.start(start1),.address_ok(address_ok1),.same_out(same_in2),
			  .reset(reset),.clk(clk));


top  part2(.cur_lift1(cur_lift2_1),.cur_lift2(cur_lift2_2),.state1(state2_1),.state2(state2_2),.same_in(same_in2),.OK(),
           .floor_address(floor_address),.up_user(up_user2),.down_user(down_user2),
           .address_user(address_user2),.start(start2),.address_ok(address_ok2),.same_out(same_in1), 
			  .reset(reset),.clk(clk));

endmodule