lift_top.v

控制两组,每组三个电梯的verilog实现

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:37:44 01/08/07
// Design Name:    
// Module Name:    lift_top
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module lift_top(lift_out,state,request,address_user,start,DESLE,address_ok,clk,reset);
input DESLE,start,address_ok,clk,reset;
input [7:0] request;
input [3:0]	address_user;
output [23:0] lift_out;	//	reg lift_out
output [1:0] state;

wire  free_out,free_in,wait_out,up_out,up_in,timeup,CLE,clear;
wire [15:0] des_cu_floor,des_user_floor,des_out,des_in;
wire [3:0] cur_out; 

register1 #(1) free (.register_out(free_out),.register_in(free_in),.clk(clk),.reset(reset),.load_enable(1'b1));
register1 #(1) up (.register_out(up_out),.register_in(up_in),.clk(clk),.reset(reset),.load_enable(1'b1));
register1 #(1) wait_r(.register_out(wait_out),.register_in(wait_in),.clk(clk),.reset(reset),.load_enable(1'b1));
register #(16) des_r (.register_out(des_out),.register_in(des_in),.clk(clk),.reset(reset),.load_enable(1'b1));

cu_lift_1  cu_lift(.wait_in(wait_in),.free_in(free_in),.up_in(up_in),.state(state),.des_floor(des_in),.CLE(CLE),.DESLE(clear),.cur_floor(cur_out),
                   .des_cu_floor(des_cu_floor),.des_user_floor(des_user_floor),
                   .up_in_f(up_out),.start(start),.bye(timeup),.reset(reset),.clk(clk));
					  
Cur_floor cur (.floor_out(cur_out),.lift_info({free_out,up_out,1'b0,wait_out}),.clk(clk),.reset(reset));


des_floor_top des(.des_flo_cu(des_cu_floor),.des_flo_user(des_user_floor),
                    .address_cu(request[7:4]),.set_cu(DESLE),.address_user(address_user),
                    .address_ok(address_ok),.DESLE(clear),.clk(clk),.reset(reset));

counter16 #(16) counter (.timeup(timeup),.time_stop(16'h64),.clk(clk),.reset(CLE));

assign 	lift_out  = {free_out,up_out,1'b0,wait_out,cur_out,des_out};
endmodule