instrmem.v

用VHDL设计具有简单MIPS功能的源码

//******************************************************************************
//
// instrmem.v
//
// the implementation for instruction memory.
//
//
//******************************************************************************

module instrmem (
	address,
	clock,
	q);
input[3:0] address;
input clock;
output[31:0] q;
reg [31:0] q;

reg [31:0] memory[0:15];
initial
begin
	memory [0] = 32'h00000820;
	memory [1] = 32'h20020004;
	memory [2] = 32'h00001820;
	memory [3] = 32'h8C240000;
	memory [4] = 32'h20210004;
	memory [5] = 32'h00641820;
	memory [6] = 32'h2042FFFF;
	memory [7] = 32'h10400003;
	memory [8] = 32'h0;
	memory [9] = 32'h08000003;
	memory [10] = 32'h0;
	memory [11] = 32'hAC230000;
	memory [12] = 32'h0800000C;
	memory [13] = 32'h0;
	memory [14] = 32'h0;
	memory [15] = 32'h0;
	
/*
	memory [0] = 32'h00000820;
	memory [1] = 32'h20020004;
	memory [2] = 32'h00001820;
	memory [3] = 32'h8C240000;
	memory [4] = 32'h20210004;
	memory [5] = 32'h00641820;
	memory [6] = 32'h2042FFFF;
	memory [7] = 32'h0;
	memory [8] = 32'h10400003;
	memory [9] = 32'h0;
	memory [10] = 32'h08000003;
	memory [11] = 32'h0;
	memory [12] = 32'hAC230000;
	memory [13] = 32'h0800000D;
	memory [14] = 32'h0;
	memory [15] = 32'h0;
*/
end

always @(posedge clock)
begin
	q = memory[address];
end
endmodule