testalu.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 20 行

// the test file for ALU
module testalu;
  reg [3:0] ALUcontrol;
  reg [31:0] ALUOpA, ALUOpB;
  wire [31:0] ALUResult;
  wire ALUZero;
  ALU alumips(ALUResult, ALUcontrol, ALUOpA, ALUOpB);
  initial
  begin
    $monitor($time,"ALUcontrol= %d,ALUOpA = %d,ALUOpB = %d,ALUResult =%d\n",ALUcontrol,ALUOpA,ALUOpB,ALUResult);
    ALUOpA = 0; ALUOpB = 0; ALUcontrol=4'b0001;
    #10 ALUOpA = 2; ALUOpB = 1;
    #10 ALUcontrol=2;
    #10 $finish;
  end
endmodule