alu.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 52 行

//******************************************************************************
//
// ALU.v
//
// The ALU performs all the arithmetic/logical integer operations 
// specified by the ALUcontrol from the decoder. 
// 
//
//******************************************************************************
`include "define.v"

module ALU (ALUResult, ALUcontrol, ALUOpA, ALUOpB);
	input [3:0]		ALUcontrol;				// Operation select
	input [31:0]	ALUOpA, ALUOpB;			// operands

	output [31:0]	ALUResult;				// result of operation

	reg [31:0]		ALUResult;
	
	always @(ALUOpA or ALUOpB or ALUcontrol)
	begin
		case (ALUcontrol)
			`aluop_add:
				ALUResult = ALUOpA + ALUOpB;
			`aluop_sub:
				ALUResult = ALUOpA - ALUOpB;
			`aluop_and:
				ALUResult = ALUOpA & ALUOpB;
			`aluop_or:
				ALUResult = ALUOpA | ALUOpB;
			`aluop_slt:
				ALUResult = (ALUOpA < ALUOpB);
			`aluop_lw:
				ALUResult = ALUOpA + ALUOpB;
			`aluop_sw:
				ALUResult = ALUOpA + ALUOpB;
			`aluop_addi:
				ALUResult = ALUOpA + ALUOpB;
			`aluop_andi:
				ALUResult = ALUOpA & ALUOpB;
			`aluop_ori:
				ALUResult = ALUOpA | ALUOpB;
			`aluop_beq:
				ALUResult = ALUOpA - ALUOpB;
			`aluop_bne:
				ALUResult = ALUOpA - ALUOpB;
			default:
				ALUResult = 32'b1;
		endcase
	end

endmodule